A LOW-LATENCY FPGA FRAMEWORK BASED ON RELIABLE UDP AND TCP RE-ASSEMBLY MIDDLEWARE

A method and system of a low-latency FPGA framework based on reliable UDP and TCP re-assembly middleware is disclosed. The need for low-latency communication in digital systems has increased drastically. The disclosed FPGA framework enables low-latency communication as a hybrid framework that suppor...

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Bibliographische Detailangaben

Hauptverfasser:	Puranik, Sunil, Nambiar, Manoj, Shah, Dhaval, Mukhekar, Sharyu Vijay, Shaikh, Ishtiyaque, Manavar, Piyush, Barve, Mahesh Damodar
Format:	Patent
Sprache:	eng ; fre ; ger
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC COMMUNICATION TECHNIQUE ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY PHYSICS TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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