A LOW-LATENCY FPGA FRAMEWORK BASED ON RELIABLE UDP AND TCP RE-ASSEMBLY MIDDLEWARE
A method and system of a low-latency FPGA framework based on reliable UDP and TCP re-assembly middleware is disclosed. The need for low-latency communication in digital systems has increased drastically. The disclosed FPGA framework enables low-latency communication as a hybrid framework that suppor...
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| creator | Puranik, Sunil Nambiar, Manoj Shah, Dhaval Mukhekar, Sharyu Vijay Shaikh, Ishtiyaque Manavar, Piyush Barve, Mahesh Damodar |
| description | A method and system of a low-latency FPGA framework based on reliable UDP and TCP re-assembly middleware is disclosed. The need for low-latency communication in digital systems has increased drastically. The disclosed FPGA framework enables low-latency communication as a hybrid framework that supports both UDP & TCP communication. As known in art, TCP provides error checking support hence making TCP more reliable as compared to UDP, while UDP is faster but not reliable. Hence the disclosed low-latency FPGA framework latency utilizes the advantage of both UDP and TCP by utilizing UDP for its speed, while switching to TCP in case of a missing sequence in UDP. Further, the disclosed system proposes a TCP re-assembly middleware architecture for processing TCP with a lower-latency, wherein the TCP re-assembly middleware is an independent middleware that is a modular and a plug-play independent middleware. |
| format | Patent |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC COMMUNICATION TECHNIQUE ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY PHYSICS TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION |
| title | A LOW-LATENCY FPGA FRAMEWORK BASED ON RELIABLE UDP AND TCP RE-ASSEMBLY MIDDLEWARE |
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