SPECULATIVE DECOMPRESSION WITHIN PROCESSOR CORE CACHES

SPECULATIVE DECOMPRESSION WITHIN PROCESSOR CORE CACHES

Methods and apparatus relating to speculative decompression within processor core caches are described. In an embodiment, decode circuitry decodes a decompression instruction into a first micro operation and a second micro operation. The first micro operation causes one or more load operations to fe...

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Hauptverfasser: Subramoney, Sreenivas, Feghali, Wajdi, Gopal, Vinodh, Gaur, Jayesh, Shanbhogue, Vedvyas, Chauhan, Adarsh
Format: Patent
Sprache:eng ; fre ; ger
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CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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creator Subramoney, Sreenivas
Feghali, Wajdi
Gopal, Vinodh
Gaur, Jayesh
Shanbhogue, Vedvyas
Chauhan, Adarsh
description Methods and apparatus relating to speculative decompression within processor core caches are described. In an embodiment, decode circuitry decodes a decompression instruction into a first micro operation and a second micro operation. The first micro operation causes one or more load operations to fetch data into a plurality of cachelines of a cache of a processor core. Decompression Engine (DE) circuitry decompresses the fetched data from the plurality of cachelines of the cache of the processor core in response to the second micro operation. The decompression instruction causes the DE circuitry to perform an out-of-order decompression of the plurality of cachelines. Other embodiments are also disclosed and claimed.
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In an embodiment, decode circuitry decodes a decompression instruction into a first micro operation and a second micro operation. The first micro operation causes one or more load operations to fetch data into a plurality of cachelines of a cache of a processor core. Decompression Engine (DE) circuitry decompresses the fetched data from the plurality of cachelines of the cache of the processor core in response to the second micro operation. The decompression instruction causes the DE circuitry to perform an out-of-order decompression of the plurality of cachelines. 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subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title SPECULATIVE DECOMPRESSION WITHIN PROCESSOR CORE CACHES
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