RECONFIGURABLE CACHE HIERARCHY FRAMEWORK FOR THE STORAGE OF FPGA BITSTREAMS

A network-based apparatus includes at least one processor and at least one memory including computer program code. The at least one memory and the computer program code are configured to, with the at least one processor, cause the network apparatus to configure a cache manager according to a cache m...

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Hauptverfasser:	LALLET, Julien, ENRICI, Andrea
Format:	Patent
Sprache:	eng ; fre ; ger
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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creator	LALLET, Julien ENRICI, Andrea
description	A network-based apparatus includes at least one processor and at least one memory including computer program code. The at least one memory and the computer program code are configured to, with the at least one processor, cause the network apparatus to configure a cache manager according to a cache management policy identified in a request from a network orchestrator, the cache manager managing a cache of a multi-level cache hierarchy, the cache storing bitstreams for configuring a programmable device.
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subjects	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
title	RECONFIGURABLE CACHE HIERARCHY FRAMEWORK FOR THE STORAGE OF FPGA BITSTREAMS
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