PERFORMING ATOMIC STORE-AND-INVALIDATE OPERATIONS IN PROCESSOR-BASED DEVICES

Performing atomic store-and-invalidate operations in processor-based devices is disclosed. In this regard, a processing element (PE) of one or more PEs of a processor-based device includes a store-and-invalidate logic circuit used by a memory access stage of an execution pipeline of the PE to perform an atomic store-and-invalidate operation. Upon receiving an indication to perform a store-and-invalidate operation (e.g., in response to a store-and-invalidate instruction execution) comprising a store address and store data, the memory access stage uses the store-and-invalidate logic circuit to write the store data to a memory location indicated by the store address, and to invalidate an instruction cache line corresponding to the store address in an instruction cache of the PE. The operations for storing data and invalidating instruction cache lines are performed as one atomic store-and-invalidate operation, such that the store-and-invalidate operation is considered successful only if both the store and invalidate operations are successful.