COMPUTE OPTIMIZATION MECHANISM FOR DEEP NEURAL NETWORKS
The present disclosure provides a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing units, including a first set of execution uni...
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creator | Galoppo von Borries, Nicolas Satish, Nadathur Rajagopalan Ashbaugh, Ben J Akhbari, Farshad Ray, Joydeep Srinivasa, Narayan Maiyuran, Subramaniam Schluessler, Travis T Feit, John H Gottschlich, Justin E Boles, Jeffery S Vaidyanathan, Karthik Surti, Prasoonkumar Nurvitadhi, Eriko Burke, Devan Hurd, Linda L Appu, Abhishek R Chen, Feng Baghsorkhi, Sara S Lake, Adam T Lin, Tsung-Han Fu, Wenyin Koker, Altug Kim, Dukhwan Sinha, Kamal Vembu, Balaji Barik, Rajkishore Mastronarde, Josh B |
description | The present disclosure provides a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing units, including a first set of execution units of a first type to process matrix instructions on a first set of operands stored in a first set of registers of the register file, wherein the first set of operands including one or more 64-bit operands and a second set of execution units of a second type, the second set of execution units being different from the first set of execution units, the second set of execution units to perform general purpose graphics processing unit, GPGPU, instructions on a second set of operands stored in a second set of registers of the register file. |
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Nurvitadhi, Eriko ; Burke, Devan ; Hurd, Linda L ; Appu, Abhishek R ; Chen, Feng ; Baghsorkhi, Sara S ; Lake, Adam T ; Lin, Tsung-Han ; Fu, Wenyin ; Koker, Altug ; Kim, Dukhwan ; Sinha, Kamal ; Vembu, Balaji ; Barik, Rajkishore ; Mastronarde, Josh B</creator><creatorcontrib>Galoppo von Borries, Nicolas ; Satish, Nadathur Rajagopalan ; Ashbaugh, Ben J ; Akhbari, Farshad ; Ray, Joydeep ; Srinivasa, Narayan ; Maiyuran, Subramaniam ; Schluessler, Travis T ; Feit, John H ; Gottschlich, Justin E ; Boles, Jeffery S ; Vaidyanathan, Karthik ; Surti, Prasoonkumar ; Nurvitadhi, Eriko ; Burke, Devan ; Hurd, Linda L ; Appu, Abhishek R ; Chen, Feng ; Baghsorkhi, Sara S ; Lake, Adam T ; Lin, Tsung-Han ; Fu, Wenyin ; Koker, Altug ; Kim, Dukhwan ; Sinha, Kamal ; Vembu, Balaji ; Barik, Rajkishore ; Mastronarde, Josh B</creatorcontrib><description>The present disclosure provides a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing units, including a first set of execution units of a first type to process matrix instructions on a first set of operands stored in a first set of registers of the register file, wherein the first set of operands including one or more 64-bit operands and a second set of execution units of a second type, the second set of execution units being different from the first set of execution units, the second set of execution units to perform general purpose graphics processing unit, GPGPU, instructions on a second set of operands stored in a second set of registers of the register file.</description><language>eng ; fre ; ger</language><subject>CALCULATING ; COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; IMAGE DATA PROCESSING OR GENERATION, IN GENERAL ; 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Farshad</creatorcontrib><creatorcontrib>Ray, Joydeep</creatorcontrib><creatorcontrib>Srinivasa, Narayan</creatorcontrib><creatorcontrib>Maiyuran, Subramaniam</creatorcontrib><creatorcontrib>Schluessler, Travis T</creatorcontrib><creatorcontrib>Feit, John H</creatorcontrib><creatorcontrib>Gottschlich, Justin E</creatorcontrib><creatorcontrib>Boles, Jeffery S</creatorcontrib><creatorcontrib>Vaidyanathan, Karthik</creatorcontrib><creatorcontrib>Surti, Prasoonkumar</creatorcontrib><creatorcontrib>Nurvitadhi, Eriko</creatorcontrib><creatorcontrib>Burke, Devan</creatorcontrib><creatorcontrib>Hurd, Linda L</creatorcontrib><creatorcontrib>Appu, Abhishek R</creatorcontrib><creatorcontrib>Chen, Feng</creatorcontrib><creatorcontrib>Baghsorkhi, Sara S</creatorcontrib><creatorcontrib>Lake, Adam T</creatorcontrib><creatorcontrib>Lin, Tsung-Han</creatorcontrib><creatorcontrib>Fu, Wenyin</creatorcontrib><creatorcontrib>Koker, Altug</creatorcontrib><creatorcontrib>Kim, Dukhwan</creatorcontrib><creatorcontrib>Sinha, Kamal</creatorcontrib><creatorcontrib>Vembu, Balaji</creatorcontrib><creatorcontrib>Barik, Rajkishore</creatorcontrib><creatorcontrib>Mastronarde, Josh B</creatorcontrib><title>COMPUTE OPTIMIZATION MECHANISM FOR DEEP NEURAL NETWORKS</title><description>The present disclosure provides a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing units, including a first set of execution units of a first type to process matrix instructions on a first set of operands stored in a first set of registers of the register file, wherein the first set of operands including one or more 64-bit operands and a second set of execution units of a second type, the second set of execution units being different from the first set of execution units, the second set of execution units to perform general purpose graphics processing unit, GPGPU, instructions on a second set of operands stored in a second set of registers of the register file.</description><subject>CALCULATING</subject><subject>COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>IMAGE DATA PROCESSING OR GENERATION, IN GENERAL</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2022</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDB39vcNCA1xVfAPCPH09YxyDPH091PwdXX2cPTzDPZVcPMPUnBxdQ1Q8HMNDXL0AVIh4f5B3sE8DKxpiTnFqbxQmptBwc01xNlDN7UgPz61uCAxOTUvtSTeNcDY0szE0tTC0dCYCCUAGL8oQA</recordid><startdate>20220309</startdate><enddate>20220309</enddate><creator>Galoppo von Borries, Nicolas</creator><creator>Satish, Nadathur Rajagopalan</creator><creator>Ashbaugh, Ben J</creator><creator>Akhbari, Farshad</creator><creator>Ray, Joydeep</creator><creator>Srinivasa, Narayan</creator><creator>Maiyuran, Subramaniam</creator><creator>Schluessler, Travis T</creator><creator>Feit, John H</creator><creator>Gottschlich, Justin E</creator><creator>Boles, Jeffery S</creator><creator>Vaidyanathan, Karthik</creator><creator>Surti, Prasoonkumar</creator><creator>Nurvitadhi, Eriko</creator><creator>Burke, Devan</creator><creator>Hurd, Linda L</creator><creator>Appu, Abhishek R</creator><creator>Chen, Feng</creator><creator>Baghsorkhi, Sara S</creator><creator>Lake, Adam T</creator><creator>Lin, Tsung-Han</creator><creator>Fu, Wenyin</creator><creator>Koker, Altug</creator><creator>Kim, Dukhwan</creator><creator>Sinha, Kamal</creator><creator>Vembu, Balaji</creator><creator>Barik, Rajkishore</creator><creator>Mastronarde, Josh B</creator><scope>EVB</scope></search><sort><creationdate>20220309</creationdate><title>COMPUTE OPTIMIZATION MECHANISM FOR DEEP NEURAL NETWORKS</title><author>Galoppo von Borries, Nicolas ; Satish, Nadathur Rajagopalan ; Ashbaugh, Ben J ; Akhbari, Farshad ; Ray, Joydeep ; Srinivasa, Narayan ; Maiyuran, Subramaniam ; Schluessler, Travis T ; Feit, John H ; Gottschlich, Justin E ; Boles, Jeffery S ; Vaidyanathan, Karthik ; Surti, Prasoonkumar ; Nurvitadhi, Eriko ; Burke, Devan ; Hurd, Linda L ; Appu, Abhishek R ; Chen, Feng ; Baghsorkhi, Sara S ; Lake, Adam T ; Lin, Tsung-Han ; Fu, Wenyin ; Koker, Altug ; Kim, Dukhwan ; Sinha, Kamal ; Vembu, Balaji ; Barik, Rajkishore ; Mastronarde, Josh B</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP3964958A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre ; ger</language><creationdate>2022</creationdate><topic>CALCULATING</topic><topic>COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>IMAGE DATA PROCESSING OR GENERATION, IN GENERAL</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>Galoppo von Borries, Nicolas</creatorcontrib><creatorcontrib>Satish, Nadathur Rajagopalan</creatorcontrib><creatorcontrib>Ashbaugh, Ben J</creatorcontrib><creatorcontrib>Akhbari, Farshad</creatorcontrib><creatorcontrib>Ray, Joydeep</creatorcontrib><creatorcontrib>Srinivasa, Narayan</creatorcontrib><creatorcontrib>Maiyuran, Subramaniam</creatorcontrib><creatorcontrib>Schluessler, Travis T</creatorcontrib><creatorcontrib>Feit, John H</creatorcontrib><creatorcontrib>Gottschlich, Justin E</creatorcontrib><creatorcontrib>Boles, Jeffery S</creatorcontrib><creatorcontrib>Vaidyanathan, Karthik</creatorcontrib><creatorcontrib>Surti, Prasoonkumar</creatorcontrib><creatorcontrib>Nurvitadhi, Eriko</creatorcontrib><creatorcontrib>Burke, Devan</creatorcontrib><creatorcontrib>Hurd, Linda L</creatorcontrib><creatorcontrib>Appu, Abhishek R</creatorcontrib><creatorcontrib>Chen, Feng</creatorcontrib><creatorcontrib>Baghsorkhi, Sara S</creatorcontrib><creatorcontrib>Lake, Adam T</creatorcontrib><creatorcontrib>Lin, Tsung-Han</creatorcontrib><creatorcontrib>Fu, Wenyin</creatorcontrib><creatorcontrib>Koker, Altug</creatorcontrib><creatorcontrib>Kim, Dukhwan</creatorcontrib><creatorcontrib>Sinha, Kamal</creatorcontrib><creatorcontrib>Vembu, Balaji</creatorcontrib><creatorcontrib>Barik, Rajkishore</creatorcontrib><creatorcontrib>Mastronarde, Josh B</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Galoppo von Borries, Nicolas</au><au>Satish, Nadathur Rajagopalan</au><au>Ashbaugh, Ben J</au><au>Akhbari, Farshad</au><au>Ray, Joydeep</au><au>Srinivasa, Narayan</au><au>Maiyuran, Subramaniam</au><au>Schluessler, Travis T</au><au>Feit, John H</au><au>Gottschlich, Justin E</au><au>Boles, Jeffery S</au><au>Vaidyanathan, Karthik</au><au>Surti, Prasoonkumar</au><au>Nurvitadhi, Eriko</au><au>Burke, Devan</au><au>Hurd, Linda L</au><au>Appu, Abhishek R</au><au>Chen, Feng</au><au>Baghsorkhi, Sara S</au><au>Lake, Adam T</au><au>Lin, Tsung-Han</au><au>Fu, Wenyin</au><au>Koker, Altug</au><au>Kim, Dukhwan</au><au>Sinha, Kamal</au><au>Vembu, Balaji</au><au>Barik, Rajkishore</au><au>Mastronarde, Josh B</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>COMPUTE OPTIMIZATION MECHANISM FOR DEEP NEURAL NETWORKS</title><date>2022-03-09</date><risdate>2022</risdate><abstract>The present disclosure provides a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing units, including a first set of execution units of a first type to process matrix instructions on a first set of operands stored in a first set of registers of the register file, wherein the first set of operands including one or more 64-bit operands and a second set of execution units of a second type, the second set of execution units being different from the first set of execution units, the second set of execution units to perform general purpose graphics processing unit, GPGPU, instructions on a second set of operands stored in a second set of registers of the register file.</abstract><oa>free_for_read</oa></addata></record> |
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language | eng ; fre ; ger |
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subjects | CALCULATING COMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING IMAGE DATA PROCESSING OR GENERATION, IN GENERAL PHYSICS |
title | COMPUTE OPTIMIZATION MECHANISM FOR DEEP NEURAL NETWORKS |
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