LAMINATED PIEZOELECTRIC DEVICE, AND A METHOD FOR MANUFACTURING THE PIEZOELECTRIC DEVICE

The occurrence of cracking in a functional layer is suppressed, while maintaining flexibility of a layered structure. The layered structure includes a polymer substrate, and a crystalline functional layer formed on the first surface of the substrate. The surface roughness of the first surface of the...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: NAGAOKA, Naoki, ISHIKAWA, Taketo, NAKAMURA, Daisuke, MACHINAGA, Hironobu, KUROSE, Manami
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator NAGAOKA, Naoki
ISHIKAWA, Taketo
NAKAMURA, Daisuke
MACHINAGA, Hironobu
KUROSE, Manami
description The occurrence of cracking in a functional layer is suppressed, while maintaining flexibility of a layered structure. The layered structure includes a polymer substrate, and a crystalline functional layer formed on the first surface of the substrate. The surface roughness of the first surface of the substrate is 3 nm or less in terms of arithmetic mean roughness (Ra).
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_EP3943292B1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>EP3943292B1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_EP3943292B13</originalsourceid><addsrcrecordid>eNrjZAj3cfT19HMMcXVRCPB0jfJ39XF1DgnydFZwcQ3zdHbVUXD0c1FwVPB1DfHwd1Fw8w9S8HX0C3VzdA4JDfL0c1cI8XDFqpGHgTUtMac4lRdKczMouLmGOHvophbkx6cWFyQmp-allsS7BhhbmhgbWRo5GRoToQQAPXQwWA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>LAMINATED PIEZOELECTRIC DEVICE, AND A METHOD FOR MANUFACTURING THE PIEZOELECTRIC DEVICE</title><source>esp@cenet</source><creator>NAGAOKA, Naoki ; ISHIKAWA, Taketo ; NAKAMURA, Daisuke ; MACHINAGA, Hironobu ; KUROSE, Manami</creator><creatorcontrib>NAGAOKA, Naoki ; ISHIKAWA, Taketo ; NAKAMURA, Daisuke ; MACHINAGA, Hironobu ; KUROSE, Manami</creatorcontrib><description>The occurrence of cracking in a functional layer is suppressed, while maintaining flexibility of a layered structure. The layered structure includes a polymer substrate, and a crystalline functional layer formed on the first surface of the substrate. The surface roughness of the first surface of the substrate is 3 nm or less in terms of arithmetic mean roughness (Ra).</description><language>eng ; fre ; ger</language><subject>ELECTRICITY ; LAYERED PRODUCTS ; LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT ORNON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM ; PERFORMING OPERATIONS ; TRANSPORTING</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20240710&amp;DB=EPODOC&amp;CC=EP&amp;NR=3943292B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20240710&amp;DB=EPODOC&amp;CC=EP&amp;NR=3943292B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>NAGAOKA, Naoki</creatorcontrib><creatorcontrib>ISHIKAWA, Taketo</creatorcontrib><creatorcontrib>NAKAMURA, Daisuke</creatorcontrib><creatorcontrib>MACHINAGA, Hironobu</creatorcontrib><creatorcontrib>KUROSE, Manami</creatorcontrib><title>LAMINATED PIEZOELECTRIC DEVICE, AND A METHOD FOR MANUFACTURING THE PIEZOELECTRIC DEVICE</title><description>The occurrence of cracking in a functional layer is suppressed, while maintaining flexibility of a layered structure. The layered structure includes a polymer substrate, and a crystalline functional layer formed on the first surface of the substrate. The surface roughness of the first surface of the substrate is 3 nm or less in terms of arithmetic mean roughness (Ra).</description><subject>ELECTRICITY</subject><subject>LAYERED PRODUCTS</subject><subject>LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT ORNON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM</subject><subject>PERFORMING OPERATIONS</subject><subject>TRANSPORTING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZAj3cfT19HMMcXVRCPB0jfJ39XF1DgnydFZwcQ3zdHbVUXD0c1FwVPB1DfHwd1Fw8w9S8HX0C3VzdA4JDfL0c1cI8XDFqpGHgTUtMac4lRdKczMouLmGOHvophbkx6cWFyQmp-allsS7BhhbmhgbWRo5GRoToQQAPXQwWA</recordid><startdate>20240710</startdate><enddate>20240710</enddate><creator>NAGAOKA, Naoki</creator><creator>ISHIKAWA, Taketo</creator><creator>NAKAMURA, Daisuke</creator><creator>MACHINAGA, Hironobu</creator><creator>KUROSE, Manami</creator><scope>EVB</scope></search><sort><creationdate>20240710</creationdate><title>LAMINATED PIEZOELECTRIC DEVICE, AND A METHOD FOR MANUFACTURING THE PIEZOELECTRIC DEVICE</title><author>NAGAOKA, Naoki ; ISHIKAWA, Taketo ; NAKAMURA, Daisuke ; MACHINAGA, Hironobu ; KUROSE, Manami</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP3943292B13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre ; ger</language><creationdate>2024</creationdate><topic>ELECTRICITY</topic><topic>LAYERED PRODUCTS</topic><topic>LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT ORNON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM</topic><topic>PERFORMING OPERATIONS</topic><topic>TRANSPORTING</topic><toplevel>online_resources</toplevel><creatorcontrib>NAGAOKA, Naoki</creatorcontrib><creatorcontrib>ISHIKAWA, Taketo</creatorcontrib><creatorcontrib>NAKAMURA, Daisuke</creatorcontrib><creatorcontrib>MACHINAGA, Hironobu</creatorcontrib><creatorcontrib>KUROSE, Manami</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>NAGAOKA, Naoki</au><au>ISHIKAWA, Taketo</au><au>NAKAMURA, Daisuke</au><au>MACHINAGA, Hironobu</au><au>KUROSE, Manami</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>LAMINATED PIEZOELECTRIC DEVICE, AND A METHOD FOR MANUFACTURING THE PIEZOELECTRIC DEVICE</title><date>2024-07-10</date><risdate>2024</risdate><abstract>The occurrence of cracking in a functional layer is suppressed, while maintaining flexibility of a layered structure. The layered structure includes a polymer substrate, and a crystalline functional layer formed on the first surface of the substrate. The surface roughness of the first surface of the substrate is 3 nm or less in terms of arithmetic mean roughness (Ra).</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng ; fre ; ger
recordid cdi_epo_espacenet_EP3943292B1
source esp@cenet
subjects ELECTRICITY
LAYERED PRODUCTS
LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT ORNON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
PERFORMING OPERATIONS
TRANSPORTING
title LAMINATED PIEZOELECTRIC DEVICE, AND A METHOD FOR MANUFACTURING THE PIEZOELECTRIC DEVICE
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-01T16%3A29%3A48IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=NAGAOKA,%20Naoki&rft.date=2024-07-10&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EEP3943292B1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true