METHOD AND APPARATUS FOR IMPROVED DATA TRANSFER BETWEEN PROCESSOR CORES

Embodiments of an interconnect apparatus enable improved signal integrity, even at high clock rates, increased bandwidth, and lower latency. In an interconnect apparatus for core arrays a sending processing core can send data An interconnect apparatus for core arrays a sending processing core can send data to a receiving core by forming a packet whose header indicates the location of the receiving core and whose pay load is the data to be sent. The packet is sent to a Data Vortex switch on the same chip as an array of processing cores and routes the packet to the receiving core first by routing the packet to the processing core array containing the receiving processing core. The Data Vortex switch then routes the packet to the receiving processor core in a processor core array. The Data Vortex switches are not crossbar switches, eliminating globally setting and resetting the Data Vortex switches as different groups of packets enter the switches. Mounting the Data Vortex switch on the same chip as the array of processing cores reduces power required and latency.