APPARATUSES, METHODS, AND SYSTEMS FOR DUAL SPATIAL PATTERN PREFETCHER
Systems, methods, and apparatuses relating to a dual spatial pattern prefetcher are described. In one embodiment, a prefetch circuit is to prefetch a cache line into a cache from a memory by tracking page and cache line accesses to the cache for a single access signature, generate a spatial bit patt...
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creator | Subramoney, Sreenivas Bera, Rahul Nori, Anant Vithal |
description | Systems, methods, and apparatuses relating to a dual spatial pattern prefetcher are described. In one embodiment, a prefetch circuit is to prefetch a cache line into a cache from a memory by tracking page and cache line accesses to the cache for a single access signature, generate a spatial bit pattern, for the cache line accesses for each page of a plurality of pages, that is shifted to a first cache line access for each page, generate a single spatial bit pattern for the single access signature for each of the spatial bit patterns that have a same spatial bit pattern to form a plurality of single spatial bit patterns, perform a logical OR operation on the plurality of single spatial bit patterns to create a first modulated bit pattern for the single access signature, perform a logical AND operation on the plurality of single spatial bit patterns to create a second modulated bit pattern for the single access signature, receive a prefetch request for the single access signature, and perform a prefetch operation for the prefetch request using the first modulated bit pattern when a threshold is not exceeded and the second modulated bit pattern when the threshold is exceeded. |
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fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_EP3796180A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>EP3796180A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_EP3796180A13</originalsourceid><addsrcrecordid>eNrjZHB1DAhwDHIMCQ12DdZR8HUN8fB3ATIc_VwUgiODQ1x9gxXc_IMUXEIdfRSCAxxDPIE0kApxDfJTCAhydXMNcfZwDeJhYE1LzClO5YXS3AwKYBnd1IL8-NTigsTk1LzUknjXAGNzSzNDCwNHQ2MilAAAMmUruQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>APPARATUSES, METHODS, AND SYSTEMS FOR DUAL SPATIAL PATTERN PREFETCHER</title><source>esp@cenet</source><creator>Subramoney, Sreenivas ; Bera, Rahul ; Nori, Anant Vithal</creator><creatorcontrib>Subramoney, Sreenivas ; Bera, Rahul ; Nori, Anant Vithal</creatorcontrib><description>Systems, methods, and apparatuses relating to a dual spatial pattern prefetcher are described. In one embodiment, a prefetch circuit is to prefetch a cache line into a cache from a memory by tracking page and cache line accesses to the cache for a single access signature, generate a spatial bit pattern, for the cache line accesses for each page of a plurality of pages, that is shifted to a first cache line access for each page, generate a single spatial bit pattern for the single access signature for each of the spatial bit patterns that have a same spatial bit pattern to form a plurality of single spatial bit patterns, perform a logical OR operation on the plurality of single spatial bit patterns to create a first modulated bit pattern for the single access signature, perform a logical AND operation on the plurality of single spatial bit patterns to create a second modulated bit pattern for the single access signature, receive a prefetch request for the single access signature, and perform a prefetch operation for the prefetch request using the first modulated bit pattern when a threshold is not exceeded and the second modulated bit pattern when the threshold is exceeded.</description><language>eng ; fre ; ger</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2021</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210324&DB=EPODOC&CC=EP&NR=3796180A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20210324&DB=EPODOC&CC=EP&NR=3796180A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Subramoney, Sreenivas</creatorcontrib><creatorcontrib>Bera, Rahul</creatorcontrib><creatorcontrib>Nori, Anant Vithal</creatorcontrib><title>APPARATUSES, METHODS, AND SYSTEMS FOR DUAL SPATIAL PATTERN PREFETCHER</title><description>Systems, methods, and apparatuses relating to a dual spatial pattern prefetcher are described. In one embodiment, a prefetch circuit is to prefetch a cache line into a cache from a memory by tracking page and cache line accesses to the cache for a single access signature, generate a spatial bit pattern, for the cache line accesses for each page of a plurality of pages, that is shifted to a first cache line access for each page, generate a single spatial bit pattern for the single access signature for each of the spatial bit patterns that have a same spatial bit pattern to form a plurality of single spatial bit patterns, perform a logical OR operation on the plurality of single spatial bit patterns to create a first modulated bit pattern for the single access signature, perform a logical AND operation on the plurality of single spatial bit patterns to create a second modulated bit pattern for the single access signature, receive a prefetch request for the single access signature, and perform a prefetch operation for the prefetch request using the first modulated bit pattern when a threshold is not exceeded and the second modulated bit pattern when the threshold is exceeded.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2021</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHB1DAhwDHIMCQ12DdZR8HUN8fB3ATIc_VwUgiODQ1x9gxXc_IMUXEIdfRSCAxxDPIE0kApxDfJTCAhydXMNcfZwDeJhYE1LzClO5YXS3AwKYBnd1IL8-NTigsTk1LzUknjXAGNzSzNDCwNHQ2MilAAAMmUruQ</recordid><startdate>20210324</startdate><enddate>20210324</enddate><creator>Subramoney, Sreenivas</creator><creator>Bera, Rahul</creator><creator>Nori, Anant Vithal</creator><scope>EVB</scope></search><sort><creationdate>20210324</creationdate><title>APPARATUSES, METHODS, AND SYSTEMS FOR DUAL SPATIAL PATTERN PREFETCHER</title><author>Subramoney, Sreenivas ; Bera, Rahul ; Nori, Anant Vithal</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP3796180A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre ; ger</language><creationdate>2021</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>Subramoney, Sreenivas</creatorcontrib><creatorcontrib>Bera, Rahul</creatorcontrib><creatorcontrib>Nori, Anant Vithal</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Subramoney, Sreenivas</au><au>Bera, Rahul</au><au>Nori, Anant Vithal</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>APPARATUSES, METHODS, AND SYSTEMS FOR DUAL SPATIAL PATTERN PREFETCHER</title><date>2021-03-24</date><risdate>2021</risdate><abstract>Systems, methods, and apparatuses relating to a dual spatial pattern prefetcher are described. In one embodiment, a prefetch circuit is to prefetch a cache line into a cache from a memory by tracking page and cache line accesses to the cache for a single access signature, generate a spatial bit pattern, for the cache line accesses for each page of a plurality of pages, that is shifted to a first cache line access for each page, generate a single spatial bit pattern for the single access signature for each of the spatial bit patterns that have a same spatial bit pattern to form a plurality of single spatial bit patterns, perform a logical OR operation on the plurality of single spatial bit patterns to create a first modulated bit pattern for the single access signature, perform a logical AND operation on the plurality of single spatial bit patterns to create a second modulated bit pattern for the single access signature, receive a prefetch request for the single access signature, and perform a prefetch operation for the prefetch request using the first modulated bit pattern when a threshold is not exceeded and the second modulated bit pattern when the threshold is exceeded.</abstract><oa>free_for_read</oa></addata></record> |
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language | eng ; fre ; ger |
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subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
title | APPARATUSES, METHODS, AND SYSTEMS FOR DUAL SPATIAL PATTERN PREFETCHER |
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