ACCELERATOR FOR SPARSE-DENSE MATRIX MULTIPLICATION

Disclosed embodiments relate to multiply-accumulate operations. In one example, a processor, comprises fetch circuitry, a plurality of registers, and execution circuitry. The fetch circuitry is to fetch a sparse-dense matrix multiplication (SDMM) instruction from a memory. The SDMM instruction has f...

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Bibliographische Detailangaben

Hauptverfasser:	Satish, Nadathur Rajagopalan, Narayanamoorthy, Srinivasan, Suprun, Alexey, Janik, Kenneth J
Format:	Patent
Sprache:	eng ; fre ; ger
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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