HARDWARE UNIT FOR PERFORMING MATRIX MULTIPLICATION WITH CLOCK GATING

Hardware units and methods to perform matrix multiplication between a first matrix of first data elements and a second matrix of second data elements. The hardware unit includes: a multiplier stage comprising a plurality of multipliers, each multiplier configured to multiply a first data element and...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	PULIMENO, Azzurra, MARTIN, Chris
Format:	Patent
Sprache:	eng ; fre ; ger
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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