SUPERCONDUCTING GATE MEMORY CIRCUIT
One embodiment includes a superconducting gate memory circuit. The circuit comprises a gate circuit configured to set a digital state as one of a first data state and a second data state in response to a presence of or absence of a write data single flux quantum, SFQ, pulse provided on a data write...
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| creator | Herr, Quentin P Burnett, Randall M |
| description | One embodiment includes a superconducting gate memory circuit. The circuit comprises a gate circuit configured to set a digital state as one of a first data state and a second data state in response to a presence of or absence of a write data single flux quantum, SFQ, pulse provided on a data write input. The circuit further comprises a storage loop coupled to the gate circuit and configured to conduct a loop current having an amplitude that is set based on the digital state. |
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The circuit comprises a gate circuit configured to set a digital state as one of a first data state and a second data state in response to a presence of or absence of a write data single flux quantum, SFQ, pulse provided on a data write input. The circuit further comprises a storage loop coupled to the gate circuit and configured to conduct a loop current having an amplitude that is set based on the digital state.</description><language>eng ; fre ; ger</language><subject>BASIC ELECTRONIC CIRCUITRY ; ELECTRICITY ; INFORMATION STORAGE ; PHYSICS ; PULSE TECHNIQUE ; STATIC STORES</subject><creationdate>2024</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240228&DB=EPODOC&CC=EP&NR=3764543B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25544,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20240228&DB=EPODOC&CC=EP&NR=3764543B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Herr, Quentin P</creatorcontrib><creatorcontrib>Burnett, Randall M</creatorcontrib><title>SUPERCONDUCTING GATE MEMORY CIRCUIT</title><description>One embodiment includes a superconducting gate memory circuit. The circuit comprises a gate circuit configured to set a digital state as one of a first data state and a second data state in response to a presence of or absence of a write data single flux quantum, SFQ, pulse provided on a data write input. The circuit further comprises a storage loop coupled to the gate circuit and configured to conduct a loop current having an amplitude that is set based on the digital state.</description><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>ELECTRICITY</subject><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>PULSE TECHNIQUE</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2024</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFAODg1wDXL293MJdQ7x9HNXcHcMcVXwdfX1D4pUcPYMcg71DOFhYE1LzClO5YXS3AwKbq4hzh66qQX58anFBYnJqXmpJfGuAcbmZiamJsZOhsZEKAEANWYing</recordid><startdate>20240228</startdate><enddate>20240228</enddate><creator>Herr, Quentin P</creator><creator>Burnett, Randall M</creator><scope>EVB</scope></search><sort><creationdate>20240228</creationdate><title>SUPERCONDUCTING GATE MEMORY CIRCUIT</title><author>Herr, Quentin P ; Burnett, Randall M</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP3764543B13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre ; ger</language><creationdate>2024</creationdate><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>ELECTRICITY</topic><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>PULSE TECHNIQUE</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>Herr, Quentin P</creatorcontrib><creatorcontrib>Burnett, Randall M</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Herr, Quentin P</au><au>Burnett, Randall M</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SUPERCONDUCTING GATE MEMORY CIRCUIT</title><date>2024-02-28</date><risdate>2024</risdate><abstract>One embodiment includes a superconducting gate memory circuit. The circuit comprises a gate circuit configured to set a digital state as one of a first data state and a second data state in response to a presence of or absence of a write data single flux quantum, SFQ, pulse provided on a data write input. The circuit further comprises a storage loop coupled to the gate circuit and configured to conduct a loop current having an amplitude that is set based on the digital state.</abstract><oa>free_for_read</oa></addata></record> |
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| language | eng ; fre ; ger |
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| subjects | BASIC ELECTRONIC CIRCUITRY ELECTRICITY INFORMATION STORAGE PHYSICS PULSE TECHNIQUE STATIC STORES |
| title | SUPERCONDUCTING GATE MEMORY CIRCUIT |
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