PERFORMANCE MANAGEMENT UNIT AIDED TIER SELECTION IN HETEROGENEOUS MEMORY

A processor including a processing core to execute an instruction prior to executing a memory allocation call; one or more last branch record (LBR) registers to store one or more recently retired branch instructions; a performance monitoring unit (PMU) comprising a logic circuit to: retrieve the one...

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Hauptverfasser:	Doshi, Kshitij, Sane, Harshad
Format:	Patent
Sprache:	eng ; fre ; ger
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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creator	Doshi, Kshitij Sane, Harshad
description	A processor including a processing core to execute an instruction prior to executing a memory allocation call; one or more last branch record (LBR) registers to store one or more recently retired branch instructions; a performance monitoring unit (PMU) comprising a logic circuit to: retrieve the one or more recently retired branch instructions from the one or more LBR registers; identify, based on the retired branch instructions, a signature of the memory allocation call; provide the signature to software to determine a memory tier to allocate memory for the memory allocation call.
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subjects	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
title	PERFORMANCE MANAGEMENT UNIT AIDED TIER SELECTION IN HETEROGENEOUS MEMORY
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