LOW POWER MODE TESTING IN AN INTEGRATED CIRCUIT
An integrated circuit includes a plurality of external terminal circuits, each having an external terminal. The integrated circuit includes a wakeup detector including a plurality of inputs. Each input of the plurality of inputs is coupled to an external terminal circuit. The wakeup detector generat...
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| creator | Jagannathan, Srikanth Abhishek, Kumar Luedeke, Thomas Henry Ambati, Venkannababu Cinque, Mark Shelton Wright, Joseph Rollin |
| description | An integrated circuit includes a plurality of external terminal circuits, each having an external terminal. The integrated circuit includes a wakeup detector including a plurality of inputs. Each input of the plurality of inputs is coupled to an external terminal circuit. The wakeup detector generates an output signal indicative of an external terminal of the plurality of external terminal circuits being placed at a wakeup voltage. The integrated circuit includes a trigger generation circuit having a plurality of outputs in which each output is coupled to an external terminal circuit to generate a wake-up voltage at an external terminal of the external terminal circuit by coupling the external terminal to a power supply terminal of the integrated circuit to generate an indication of the external terminal being at the wakeup voltage at the wakeup detector when at least a portion of the integrated circuit is in a low power mode. |
| format | Patent |
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The integrated circuit includes a trigger generation circuit having a plurality of outputs in which each output is coupled to an external terminal circuit to generate a wake-up voltage at an external terminal of the external terminal circuit by coupling the external terminal to a power supply terminal of the integrated circuit to generate an indication of the external terminal being at the wakeup voltage at the wakeup detector when at least a portion of the integrated circuit is in a low power mode.</description><language>eng ; fre ; ger</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2020</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20200909&DB=EPODOC&CC=EP&NR=3705980A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20200909&DB=EPODOC&CC=EP&NR=3705980A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Jagannathan, Srikanth</creatorcontrib><creatorcontrib>Abhishek, Kumar</creatorcontrib><creatorcontrib>Luedeke, Thomas Henry</creatorcontrib><creatorcontrib>Ambati, Venkannababu</creatorcontrib><creatorcontrib>Cinque, Mark Shelton</creatorcontrib><creatorcontrib>Wright, Joseph Rollin</creatorcontrib><title>LOW POWER MODE TESTING IN AN INTEGRATED CIRCUIT</title><description>An integrated circuit includes a plurality of external terminal circuits, each having an external terminal. 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The integrated circuit includes a trigger generation circuit having a plurality of outputs in which each output is coupled to an external terminal circuit to generate a wake-up voltage at an external terminal of the external terminal circuit by coupling the external terminal to a power supply terminal of the integrated circuit to generate an indication of the external terminal being at the wakeup voltage at the wakeup detector when at least a portion of the integrated circuit is in a low power mode.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2020</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZND38Q9XCPAPdw1S8PV3cVUIcQ0O8fRzV_D0U3D0A5Ihru5BjiGuLgrOnkHOoZ4hPAysaYk5xam8UJqbQcHNNcTZQze1ID8-tbggMTk1L7Uk3jXA2NzA1NLCwNHQmAglAK9xJYA</recordid><startdate>20200909</startdate><enddate>20200909</enddate><creator>Jagannathan, Srikanth</creator><creator>Abhishek, Kumar</creator><creator>Luedeke, Thomas Henry</creator><creator>Ambati, Venkannababu</creator><creator>Cinque, Mark Shelton</creator><creator>Wright, Joseph Rollin</creator><scope>EVB</scope></search><sort><creationdate>20200909</creationdate><title>LOW POWER MODE TESTING IN AN INTEGRATED CIRCUIT</title><author>Jagannathan, Srikanth ; Abhishek, Kumar ; Luedeke, Thomas Henry ; Ambati, Venkannababu ; Cinque, Mark Shelton ; Wright, Joseph Rollin</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP3705980A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre ; ger</language><creationdate>2020</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>Jagannathan, Srikanth</creatorcontrib><creatorcontrib>Abhishek, Kumar</creatorcontrib><creatorcontrib>Luedeke, Thomas Henry</creatorcontrib><creatorcontrib>Ambati, Venkannababu</creatorcontrib><creatorcontrib>Cinque, Mark Shelton</creatorcontrib><creatorcontrib>Wright, Joseph Rollin</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Jagannathan, Srikanth</au><au>Abhishek, Kumar</au><au>Luedeke, Thomas Henry</au><au>Ambati, Venkannababu</au><au>Cinque, Mark Shelton</au><au>Wright, Joseph Rollin</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>LOW POWER MODE TESTING IN AN INTEGRATED CIRCUIT</title><date>2020-09-09</date><risdate>2020</risdate><abstract>An integrated circuit includes a plurality of external terminal circuits, each having an external terminal. The integrated circuit includes a wakeup detector including a plurality of inputs. Each input of the plurality of inputs is coupled to an external terminal circuit. The wakeup detector generates an output signal indicative of an external terminal of the plurality of external terminal circuits being placed at a wakeup voltage. The integrated circuit includes a trigger generation circuit having a plurality of outputs in which each output is coupled to an external terminal circuit to generate a wake-up voltage at an external terminal of the external terminal circuit by coupling the external terminal to a power supply terminal of the integrated circuit to generate an indication of the external terminal being at the wakeup voltage at the wakeup detector when at least a portion of the integrated circuit is in a low power mode.</abstract><oa>free_for_read</oa></addata></record> |
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| language | eng ; fre ; ger |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | LOW POWER MODE TESTING IN AN INTEGRATED CIRCUIT |
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