DIRECTED AND INTERCONNECTED GRID DATAFLOW ARCHITECTURE

DIRECTED AND INTERCONNECTED GRID DATAFLOW ARCHITECTURE

A computing grid including an interconnect network including input ports and output ports; a plurality of egress ports; a plurality of configurable data routing junctions; a plurality of logical elements interconnected using the plurality of configurable data routing junctions; a plurality of ingres...

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Hauptverfasser: RAZ, Elad, TAYARI, Ilan
Format: Patent
Sprache:eng ; fre ; ger
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creator RAZ, Elad
TAYARI, Ilan
description A computing grid including an interconnect network including input ports and output ports; a plurality of egress ports; a plurality of configurable data routing junctions; a plurality of logical elements interconnected using the plurality of configurable data routing junctions; a plurality of ingress ports. In an embodiment at least one compute graph is projected onto the computing grid as a configuration of various elements of the computing grid.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_EP3682353A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>EP3682353A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_EP3682353A13</originalsourceid><addsrcrecordid>eNrjZDBz8QxydQ5xdVFw9HNR8PQLcQ1y9vfzgwi5B3m6KLg4hji6-fiHKzgGOXt4hgBlQoNceRhY0xJzilN5oTQ3g4Kba4izh25qQX58anFBYnJqXmpJvGuAsZmFkbGpsaOhMRFKAMIvJ4g</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>DIRECTED AND INTERCONNECTED GRID DATAFLOW ARCHITECTURE</title><source>esp@cenet</source><creator>RAZ, Elad ; TAYARI, Ilan</creator><creatorcontrib>RAZ, Elad ; TAYARI, Ilan</creatorcontrib><description>A computing grid including an interconnect network including input ports and output ports; a plurality of egress ports; a plurality of configurable data routing junctions; a plurality of logical elements interconnected using the plurality of configurable data routing junctions; a plurality of ingress ports. In an embodiment at least one compute graph is projected onto the computing grid as a configuration of various elements of the computing grid.</description><language>eng ; fre ; ger</language><creationdate>2020</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20200722&amp;DB=EPODOC&amp;CC=EP&amp;NR=3682353A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76516</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20200722&amp;DB=EPODOC&amp;CC=EP&amp;NR=3682353A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>RAZ, Elad</creatorcontrib><creatorcontrib>TAYARI, Ilan</creatorcontrib><title>DIRECTED AND INTERCONNECTED GRID DATAFLOW ARCHITECTURE</title><description>A computing grid including an interconnect network including input ports and output ports; a plurality of egress ports; a plurality of configurable data routing junctions; a plurality of logical elements interconnected using the plurality of configurable data routing junctions; a plurality of ingress ports. In an embodiment at least one compute graph is projected onto the computing grid as a configuration of various elements of the computing grid.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2020</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDBz8QxydQ5xdVFw9HNR8PQLcQ1y9vfzgwi5B3m6KLg4hji6-fiHKzgGOXt4hgBlQoNceRhY0xJzilN5oTQ3g4Kba4izh25qQX58anFBYnJqXmpJvGuAsZmFkbGpsaOhMRFKAMIvJ4g</recordid><startdate>20200722</startdate><enddate>20200722</enddate><creator>RAZ, Elad</creator><creator>TAYARI, Ilan</creator><scope>EVB</scope></search><sort><creationdate>20200722</creationdate><title>DIRECTED AND INTERCONNECTED GRID DATAFLOW ARCHITECTURE</title><author>RAZ, Elad ; TAYARI, Ilan</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP3682353A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre ; ger</language><creationdate>2020</creationdate><toplevel>online_resources</toplevel><creatorcontrib>RAZ, Elad</creatorcontrib><creatorcontrib>TAYARI, Ilan</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>RAZ, Elad</au><au>TAYARI, Ilan</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>DIRECTED AND INTERCONNECTED GRID DATAFLOW ARCHITECTURE</title><date>2020-07-22</date><risdate>2020</risdate><abstract>A computing grid including an interconnect network including input ports and output ports; a plurality of egress ports; a plurality of configurable data routing junctions; a plurality of logical elements interconnected using the plurality of configurable data routing junctions; a plurality of ingress ports. In an embodiment at least one compute graph is projected onto the computing grid as a configuration of various elements of the computing grid.</abstract><oa>free_for_read</oa></addata></record>
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title DIRECTED AND INTERCONNECTED GRID DATAFLOW ARCHITECTURE
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-19T01%3A14%3A55IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=RAZ,%20Elad&rft.date=2020-07-22&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EEP3682353A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true