ENSURING A CORRECT PROGRAM SEQUENCE IN A DUAL-PROCESSOR ARCHITECTURE

A method of ensuring a correct program sequence in a dual-Processor module that includes Processor A and Processor B. Processor A and Processor B are both coupled to a common memory. Processor A and Processor B each execute a first safety program and each generate an instruction stream therefrom. At...

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Bibliographische Detailangaben

Hauptverfasser:	FOOSE, Alan, DEHAAS, Drew Christian, VAN WENSEN, Aad, BEERENS, Anton, FARMER, Jonathan
Format:	Patent
Sprache:	eng ; fre ; ger
Schlagworte:	CALCULATING COMPUTING CONTROL OR REGULATING SYSTEMS IN GENERAL CONTROLLING COUNTING ELECTRIC DIGITAL DATA PROCESSING FUNCTIONAL ELEMENTS OF SUCH SYSTEMS MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS ORELEMENTS PHYSICS REGULATING
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