CLOCK DISTRIBUTION AND GENERATION ARCHITECTURE FOR LOGIC TILES OF AN INTEGRATED CIRCUIT AND METHOD OF OPERATING SAME

An integrated circuit comprising an array of logic tiles, arranged in an array of rows and columns. The array of logic tiles includes a first logic tile to receive a first external clock signal wherein each logic tile of a first plurality of logic tiles generates the tile clock using (i) the first e...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	WANG, Cheng, C, NATU, Nitish, U
Format:	Patent
Sprache:	eng ; fre ; ger
Schlagworte:	BASIC ELECTRONIC CIRCUITRY ELECTRICITY INFORMATION STORAGE PHYSICS PULSE TECHNIQUE STATIC STORES
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!