METHOD AND SYSTEM FOR OUTPUT LATCH BASED DATA BUS FAILURE MITIGATION

A data bus system includes a processor (20) having a data output and a transceiver (50) connecting the data output to a data bus. The transceiver includes a bus-hold circuit (52) configured to maintain a latest value of the data output. At least one output latch (60) connects the data bus to at leas...

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1. Verfasser:	HOEGBERG, Lon R
Format:	Patent
Sprache:	eng ; fre ; ger
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC COMMUNICATION TECHNIQUE ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY PHYSICS TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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creator	HOEGBERG, Lon R
description	A data bus system includes a processor (20) having a data output and a transceiver (50) connecting the data output to a data bus. The transceiver includes a bus-hold circuit (52) configured to maintain a latest value of the data output. At least one output latch (60) connects the data bus to at least one corresponding controlled system (30).
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language	eng ; fre ; ger
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subjects	CALCULATING COMPUTING COUNTING ELECTRIC COMMUNICATION TECHNIQUE ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY PHYSICS TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
title	METHOD AND SYSTEM FOR OUTPUT LATCH BASED DATA BUS FAILURE MITIGATION
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