APPARATUSES AND METHODS FOR A PROCESSOR ARCHITECTURE

Embodiments of an invention a processor architecture are disclosed. In an embodiment, a processor includes a decoder, an execution unit, a coherent cache, and an interconnect. The decoder is to decode an instruction to zero a cache line. The execution unit is to issue a write command to initiate a c...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	SINGHAL, Ronak, RAPPOPORT, Lihu, OULD-AHMED-VALL, Elmoustapha, HUFF, Thomas R, CORBAL, Jesus, TOLL, Bret L, CHAPPELL, Robert S, HUGHES, Christopher J, PAPWORTH, David, SOTOUDEH, Seyed Yahya, ALLEN, James D, GUNTHER, Stephen H, BRANDT, Jason W, GUY, Buford M, GROCHOWSKI, Edward T
Format:	Patent
Sprache:	eng ; fre ; ger
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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