SEMICONDUCTOR INTEGRATED CIRCUITRY

Semiconductor integrated circuitry, having a layered structure formed on a substrate, the layered structure comprising a plurality of metal layers and via layers sandwiched between adjacent said metal layers, an upwards direction being defined through the layers away from the substrate, wherein: a capacitor is formed from metal structures implemented in at least first, second and third metal layers ordered in the upwards direction; the metal structures comprise arrangements of strips having widths parallel to the layers, the widths being within one of three ranges of widths, the ranges comprising a lower range of widths, an intermediate range of widths comprising widths larger than those in the lower range of widths, and a higher range of widths comprising widths larger than those in the intermediate range of widths; the strips formed in the first layer are organised into at least one first comb arrangement having a base strip and a plurality of finger strips extending from the base strip, the widths of the strips formed in the first layer being in the lower range of widths; the strips formed in the second layer are organised into at least one second comb arrangement having a base strip and a plurality of finger strips extending from the base strip, the widths of the finger strips formed in the second layer being in the lower range of widths, and the width of each base strip formed in the second layer being in the intermediate range of widths; and the strips formed in the third layer have widths in the higher range of widths.