CROSS POINT MEMORY CONTROL

CROSS POINT MEMORY CONTROL

The present disclosure relates to phase change memory control. An apparatus includes a memory controller. The memory controller includes a word line (WL) control module and a bit line (BL) control module. The memory controller is to determine a WL address based, at least in part, on a received memor...

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Hauptverfasser: GULIANI, Sandeep K, PANGAL, Kiran, TAUB, Mase J, ZENG, Raymond W
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
INFORMATION STORAGE
PHYSICS
STATIC STORES
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creator GULIANI, Sandeep K
PANGAL, Kiran
TAUB, Mase J
ZENG, Raymond W
description The present disclosure relates to phase change memory control. An apparatus includes a memory controller. The memory controller includes a word line (WL) control module and a bit line (BL) control module. The memory controller is to determine a WL address based, at least in part, on a received memory address. The memory controller is further to determine a BL address. The apparatus further includes a parameter selection module to select a value of a control parameter based, at least in part, on at least one of the WL address and/or the BL address.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_EP3503109B1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>EP3503109B1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_EP3503109B13</originalsourceid><addsrcrecordid>eNrjZJByDvIPDlYI8Pf0C1HwdfX1D4pUcPb3Cwny9-FhYE1LzClO5YXS3AwKbq4hzh66qQX58anFBYnJqXmpJfGuAcamBsaGBpZOhsZEKAEABvEgAw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>CROSS POINT MEMORY CONTROL</title><source>esp@cenet</source><creator>GULIANI, Sandeep K ; PANGAL, Kiran ; TAUB, Mase J ; ZENG, Raymond W</creator><creatorcontrib>GULIANI, Sandeep K ; PANGAL, Kiran ; TAUB, Mase J ; ZENG, Raymond W</creatorcontrib><description>The present disclosure relates to phase change memory control. An apparatus includes a memory controller. The memory controller includes a word line (WL) control module and a bit line (BL) control module. The memory controller is to determine a WL address based, at least in part, on a received memory address. The memory controller is further to determine a BL address. The apparatus further includes a parameter selection module to select a value of a control parameter based, at least in part, on at least one of the WL address and/or the BL address.</description><language>eng ; fre ; ger</language><subject>INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2022</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20220504&amp;DB=EPODOC&amp;CC=EP&amp;NR=3503109B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20220504&amp;DB=EPODOC&amp;CC=EP&amp;NR=3503109B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>GULIANI, Sandeep K</creatorcontrib><creatorcontrib>PANGAL, Kiran</creatorcontrib><creatorcontrib>TAUB, Mase J</creatorcontrib><creatorcontrib>ZENG, Raymond W</creatorcontrib><title>CROSS POINT MEMORY CONTROL</title><description>The present disclosure relates to phase change memory control. An apparatus includes a memory controller. The memory controller includes a word line (WL) control module and a bit line (BL) control module. The memory controller is to determine a WL address based, at least in part, on a received memory address. The memory controller is further to determine a BL address. The apparatus further includes a parameter selection module to select a value of a control parameter based, at least in part, on at least one of the WL address and/or the BL address.</description><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2022</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZJByDvIPDlYI8Pf0C1HwdfX1D4pUcPb3Cwny9-FhYE1LzClO5YXS3AwKbq4hzh66qQX58anFBYnJqXmpJfGuAcamBsaGBpZOhsZEKAEABvEgAw</recordid><startdate>20220504</startdate><enddate>20220504</enddate><creator>GULIANI, Sandeep K</creator><creator>PANGAL, Kiran</creator><creator>TAUB, Mase J</creator><creator>ZENG, Raymond W</creator><scope>EVB</scope></search><sort><creationdate>20220504</creationdate><title>CROSS POINT MEMORY CONTROL</title><author>GULIANI, Sandeep K ; PANGAL, Kiran ; TAUB, Mase J ; ZENG, Raymond W</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP3503109B13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre ; ger</language><creationdate>2022</creationdate><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>GULIANI, Sandeep K</creatorcontrib><creatorcontrib>PANGAL, Kiran</creatorcontrib><creatorcontrib>TAUB, Mase J</creatorcontrib><creatorcontrib>ZENG, Raymond W</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>GULIANI, Sandeep K</au><au>PANGAL, Kiran</au><au>TAUB, Mase J</au><au>ZENG, Raymond W</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>CROSS POINT MEMORY CONTROL</title><date>2022-05-04</date><risdate>2022</risdate><abstract>The present disclosure relates to phase change memory control. An apparatus includes a memory controller. The memory controller includes a word line (WL) control module and a bit line (BL) control module. The memory controller is to determine a WL address based, at least in part, on a received memory address. The memory controller is further to determine a BL address. The apparatus further includes a parameter selection module to select a value of a control parameter based, at least in part, on at least one of the WL address and/or the BL address.</abstract><oa>free_for_read</oa></addata></record>
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subjects INFORMATION STORAGE
PHYSICS
STATIC STORES
title CROSS POINT MEMORY CONTROL
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