SEMICONDUCTOR PACKAGE WITH AIR CAVITY

Embodiments of chip-package and corresponding methods of manufacture are provided. In an embodiment of a chip-package, the chip-package includes: a carrier having a first side and a second side opposing the first side; a first chip coupled to the first side of the carrier; a second chip coupled to t...

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Hauptverfasser: KUEK, Hsieh Ting, ABDUL WAHID, Junny, OTHMAN, Nurfarena, CHIANG, Chau Fatt, LEE, Chee Hong, CHONG, Hock Heng, CHUA, Kok Yau, TUAZON BERNARDEZ, April Coleen, CHIN, Kon Hoe, SCHMALZL, Stefan, LIEW, Soon Lee, POK, Pei Luan, REISS, Werner, BAKAR, Roslie Saini bin
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Sprache:eng ; fre ; ger
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creator KUEK, Hsieh Ting
ABDUL WAHID, Junny
OTHMAN, Nurfarena
CHIANG, Chau Fatt
LEE, Chee Hong
CHONG, Hock Heng
CHUA, Kok Yau
TUAZON BERNARDEZ, April Coleen
CHIN, Kon Hoe
SCHMALZL, Stefan
LIEW, Soon Lee
POK, Pei Luan
REISS, Werner
BAKAR, Roslie Saini bin
description Embodiments of chip-package and corresponding methods of manufacture are provided. In an embodiment of a chip-package, the chip-package includes: a carrier having a first side and a second side opposing the first side; a first chip coupled to the first side of the carrier; a second chip coupled to the second side of the carrier; an encapsulation with a first portion, which at least partially encloses the first chip on the first side of the carrier, and a second portion, which at least partially encloses the second chip on the second side of the carrier; a via extending through the first portion of the encapsulation, the carrier and the second portion of the encapsulation; and an electrically conductive material at least partly covering a sidewall of the via in the first portion or the second portion of the encapsulation, to electrically contact the carrier at either side.
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In an embodiment of a chip-package, the chip-package includes: a carrier having a first side and a second side opposing the first side; a first chip coupled to the first side of the carrier; a second chip coupled to the second side of the carrier; an encapsulation with a first portion, which at least partially encloses the first chip on the first side of the carrier, and a second portion, which at least partially encloses the second chip on the second side of the carrier; a via extending through the first portion of the encapsulation, the carrier and the second portion of the encapsulation; and an electrically conductive material at least partly covering a sidewall of the via in the first portion or the second portion of the encapsulation, to electrically contact the carrier at either side.</description><language>eng ; fre ; ger</language><subject>MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICALDEVICES ; MICROSTRUCTURAL TECHNOLOGY ; PERFORMING OPERATIONS ; PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTUREOR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS ; TRANSPORTING</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20190612&amp;DB=EPODOC&amp;CC=EP&amp;NR=3495318A2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20190612&amp;DB=EPODOC&amp;CC=EP&amp;NR=3495318A2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KUEK, Hsieh Ting</creatorcontrib><creatorcontrib>ABDUL WAHID, Junny</creatorcontrib><creatorcontrib>OTHMAN, Nurfarena</creatorcontrib><creatorcontrib>CHIANG, Chau Fatt</creatorcontrib><creatorcontrib>LEE, Chee Hong</creatorcontrib><creatorcontrib>CHONG, Hock Heng</creatorcontrib><creatorcontrib>CHUA, Kok Yau</creatorcontrib><creatorcontrib>TUAZON BERNARDEZ, April Coleen</creatorcontrib><creatorcontrib>CHIN, Kon Hoe</creatorcontrib><creatorcontrib>SCHMALZL, Stefan</creatorcontrib><creatorcontrib>LIEW, Soon Lee</creatorcontrib><creatorcontrib>POK, Pei Luan</creatorcontrib><creatorcontrib>REISS, Werner</creatorcontrib><creatorcontrib>BAKAR, Roslie Saini bin</creatorcontrib><title>SEMICONDUCTOR PACKAGE WITH AIR CAVITY</title><description>Embodiments of chip-package and corresponding methods of manufacture are provided. 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language eng ; fre ; ger
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subjects MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICALDEVICES
MICROSTRUCTURAL TECHNOLOGY
PERFORMING OPERATIONS
PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTUREOR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
TRANSPORTING
title SEMICONDUCTOR PACKAGE WITH AIR CAVITY
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