SEMICONDUCTOR DEVICE WITH EDGE TERMINATION STRUCTURE AND METHOD OF MANUFACTURE
This disclosure relates to a semiconductor device structure and method of manufacturing a semiconductor device. The semiconductor device structure comprises a semiconductor substrate (106) having an edge region laterally separated from a device region; an edge termination structure arranged on the s...
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| creator | Roever, Martin Habenicht, Soenke Berglund, Stefan Bae, Seong-Woo |
| description | This disclosure relates to a semiconductor device structure and method of manufacturing a semiconductor device. The semiconductor device structure comprises a semiconductor substrate (106) having an edge region laterally separated from a device region; an edge termination structure arranged on the semiconductor substrate; wherein the edge termination structure comprises: a first oxide layer (114) arranged on the substrate to extend from the active region to the edge region; a second oxdide layer (116) on the first oxide layer (114); a third oxide layer or a first isolation layer (118) arranged on the first and second oxide layers; and a metal layer (104) arranged to at least partially cover the isolation layer and wherein the metal layer is further arranged to extend from the isolation layer to contact the edge region. |
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The semiconductor device structure comprises a semiconductor substrate (106) having an edge region laterally separated from a device region; an edge termination structure arranged on the semiconductor substrate; wherein the edge termination structure comprises: a first oxide layer (114) arranged on the substrate to extend from the active region to the edge region; a second oxdide layer (116) on the first oxide layer (114); a third oxide layer or a first isolation layer (118) arranged on the first and second oxide layers; and a metal layer (104) arranged to at least partially cover the isolation layer and wherein the metal layer is further arranged to extend from the isolation layer to contact the edge region.</description><language>eng ; fre ; ger</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190529&DB=EPODOC&CC=EP&NR=3490006A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76294</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20190529&DB=EPODOC&CC=EP&NR=3490006A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Roever, Martin</creatorcontrib><creatorcontrib>Habenicht, Soenke</creatorcontrib><creatorcontrib>Berglund, Stefan</creatorcontrib><creatorcontrib>Bae, Seong-Woo</creatorcontrib><title>SEMICONDUCTOR DEVICE WITH EDGE TERMINATION STRUCTURE AND METHOD OF MANUFACTURE</title><description>This disclosure relates to a semiconductor device structure and method of manufacturing a semiconductor device. The semiconductor device structure comprises a semiconductor substrate (106) having an edge region laterally separated from a device region; an edge termination structure arranged on the semiconductor substrate; wherein the edge termination structure comprises: a first oxide layer (114) arranged on the substrate to extend from the active region to the edge region; a second oxdide layer (116) on the first oxide layer (114); a third oxide layer or a first isolation layer (118) arranged on the first and second oxide layers; and a metal layer (104) arranged to at least partially cover the isolation layer and wherein the metal layer is further arranged to extend from the isolation layer to contact the edge region.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyrEKwjAQgOEsDlJ9h3sBIVIRHI_kYjLkIunFjqVInKQW6vujiA_g9A__t1bcUQwmsS1GUgZL12AI-iAeyJ4JhHIMjBISQyf5o0omQLYQSXyykBxE5OLwezZqdR8fS93-2ihwJMbv6vwc6jKPtzrV10CX9nDSWh9x3_5B3tsALkg</recordid><startdate>20190529</startdate><enddate>20190529</enddate><creator>Roever, Martin</creator><creator>Habenicht, Soenke</creator><creator>Berglund, Stefan</creator><creator>Bae, Seong-Woo</creator><scope>EVB</scope></search><sort><creationdate>20190529</creationdate><title>SEMICONDUCTOR DEVICE WITH EDGE TERMINATION STRUCTURE AND METHOD OF MANUFACTURE</title><author>Roever, Martin ; Habenicht, Soenke ; Berglund, Stefan ; Bae, Seong-Woo</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP3490006A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre ; ger</language><creationdate>2019</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Roever, Martin</creatorcontrib><creatorcontrib>Habenicht, Soenke</creatorcontrib><creatorcontrib>Berglund, Stefan</creatorcontrib><creatorcontrib>Bae, Seong-Woo</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Roever, Martin</au><au>Habenicht, Soenke</au><au>Berglund, Stefan</au><au>Bae, Seong-Woo</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR DEVICE WITH EDGE TERMINATION STRUCTURE AND METHOD OF MANUFACTURE</title><date>2019-05-29</date><risdate>2019</risdate><abstract>This disclosure relates to a semiconductor device structure and method of manufacturing a semiconductor device. The semiconductor device structure comprises a semiconductor substrate (106) having an edge region laterally separated from a device region; an edge termination structure arranged on the semiconductor substrate; wherein the edge termination structure comprises: a first oxide layer (114) arranged on the substrate to extend from the active region to the edge region; a second oxdide layer (116) on the first oxide layer (114); a third oxide layer or a first isolation layer (118) arranged on the first and second oxide layers; and a metal layer (104) arranged to at least partially cover the isolation layer and wherein the metal layer is further arranged to extend from the isolation layer to contact the edge region.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | SEMICONDUCTOR DEVICE WITH EDGE TERMINATION STRUCTURE AND METHOD OF MANUFACTURE |
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