GATE STACK FOR HETEROSTRUCTURE DEVICE

GATE STACK FOR HETEROSTRUCTURE DEVICE

A heterostructure semiconductor device includes a first active layer (102) and a second active layer (106) disposed on the first active layer. A two-dimensional electron gas layer (104) is formed between the first and second active layers. A sandwich gate dielectric layer structure (113) is disposed...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
1. Verfasser: Ramdani, Jamal
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator Ramdani, Jamal
description A heterostructure semiconductor device includes a first active layer (102) and a second active layer (106) disposed on the first active layer. A two-dimensional electron gas layer (104) is formed between the first and second active layers. A sandwich gate dielectric layer structure (113) is disposed on the second active layer. A passivation layer (114) is disposed over the sandwich gate dielectric layer structure. A gate (116) extends through the passivation layer to the sandwich gate dielectric layer structure. First (118) and second (120) ohmic contacts electrically connected to the second active layer. The first and second ohmic contacts are laterally spaced-apart, with the gate being disposed between the first and second ohmic contacts.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_EP3480854A2</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>EP3480854A2</sourcerecordid><originalsourceid>FETCH-epo_espacenet_EP3480854A23</originalsourceid><addsrcrecordid>eNrjZFB1dwxxVQgOcXT2VnDzD1LwcA1xDfIPDgkKdQ4JDXJVcHEN83R25WFgTUvMKU7lhdLcDApuriHOHrqpBfnxqcUFicmpeakl8a4BxiYWBhamJo5GxkQoAQBhZyL8</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>GATE STACK FOR HETEROSTRUCTURE DEVICE</title><source>esp@cenet</source><creator>Ramdani, Jamal</creator><creatorcontrib>Ramdani, Jamal</creatorcontrib><description>A heterostructure semiconductor device includes a first active layer (102) and a second active layer (106) disposed on the first active layer. A two-dimensional electron gas layer (104) is formed between the first and second active layers. A sandwich gate dielectric layer structure (113) is disposed on the second active layer. A passivation layer (114) is disposed over the sandwich gate dielectric layer structure. A gate (116) extends through the passivation layer to the sandwich gate dielectric layer structure. First (118) and second (120) ohmic contacts electrically connected to the second active layer. The first and second ohmic contacts are laterally spaced-apart, with the gate being disposed between the first and second ohmic contacts.</description><language>eng ; fre ; ger</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20190508&amp;DB=EPODOC&amp;CC=EP&amp;NR=3480854A2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20190508&amp;DB=EPODOC&amp;CC=EP&amp;NR=3480854A2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Ramdani, Jamal</creatorcontrib><title>GATE STACK FOR HETEROSTRUCTURE DEVICE</title><description>A heterostructure semiconductor device includes a first active layer (102) and a second active layer (106) disposed on the first active layer. A two-dimensional electron gas layer (104) is formed between the first and second active layers. A sandwich gate dielectric layer structure (113) is disposed on the second active layer. A passivation layer (114) is disposed over the sandwich gate dielectric layer structure. A gate (116) extends through the passivation layer to the sandwich gate dielectric layer structure. First (118) and second (120) ohmic contacts electrically connected to the second active layer. The first and second ohmic contacts are laterally spaced-apart, with the gate being disposed between the first and second ohmic contacts.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFB1dwxxVQgOcXT2VnDzD1LwcA1xDfIPDgkKdQ4JDXJVcHEN83R25WFgTUvMKU7lhdLcDApuriHOHrqpBfnxqcUFicmpeakl8a4BxiYWBhamJo5GxkQoAQBhZyL8</recordid><startdate>20190508</startdate><enddate>20190508</enddate><creator>Ramdani, Jamal</creator><scope>EVB</scope></search><sort><creationdate>20190508</creationdate><title>GATE STACK FOR HETEROSTRUCTURE DEVICE</title><author>Ramdani, Jamal</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP3480854A23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre ; ger</language><creationdate>2019</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>Ramdani, Jamal</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Ramdani, Jamal</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>GATE STACK FOR HETEROSTRUCTURE DEVICE</title><date>2019-05-08</date><risdate>2019</risdate><abstract>A heterostructure semiconductor device includes a first active layer (102) and a second active layer (106) disposed on the first active layer. A two-dimensional electron gas layer (104) is formed between the first and second active layers. A sandwich gate dielectric layer structure (113) is disposed on the second active layer. A passivation layer (114) is disposed over the sandwich gate dielectric layer structure. A gate (116) extends through the passivation layer to the sandwich gate dielectric layer structure. First (118) and second (120) ohmic contacts electrically connected to the second active layer. The first and second ohmic contacts are laterally spaced-apart, with the gate being disposed between the first and second ohmic contacts.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng ; fre ; ger
recordid cdi_epo_espacenet_EP3480854A2
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title GATE STACK FOR HETEROSTRUCTURE DEVICE
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-12T01%3A28%3A23IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Ramdani,%20Jamal&rft.date=2019-05-08&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EEP3480854A2%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true