TOP-SIDE CONNECTOR INTERFACE FOR PROCESSOR PACKAGING

TOP-SIDE CONNECTOR INTERFACE FOR PROCESSOR PACKAGING

An apparatus is provided which comprises: a processor die; a processor substrate having a region extended away from the processor die, wherein the processor die is mounted on the processor substrate, wherein the extended region has at least one signal interface which is connectable to a top-side con...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: AOKI, Russell S, THIBADO, Jonathan W, SMALLEY, Jeffory L
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator AOKI, Russell S
THIBADO, Jonathan W
SMALLEY, Jeffory L
description An apparatus is provided which comprises: a processor die; a processor substrate having a region extended away from the processor die, wherein the processor die is mounted on the processor substrate, wherein the extended region has at least one signal interface which is connectable to a top-side connector; and an interposer coupled to the processor substrate and a motherboard.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_EP3465753A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>EP3465753A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_EP3465753A13</originalsourceid><addsrcrecordid>eNrjZDAJ8Q_QDfZ0cVVw9vfzc3UO8Q9S8PQLcQ1yc3R2VXAD8gKC_J1dg4NBLEdnb0d3Tz93HgbWtMSc4lReKM3NoODmGuLsoZtakB-fWlyQmJyal1oS7xpgbGJmam5q7GhoTIQSAIGBJxI</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>TOP-SIDE CONNECTOR INTERFACE FOR PROCESSOR PACKAGING</title><source>esp@cenet</source><creator>AOKI, Russell S ; THIBADO, Jonathan W ; SMALLEY, Jeffory L</creator><creatorcontrib>AOKI, Russell S ; THIBADO, Jonathan W ; SMALLEY, Jeffory L</creatorcontrib><description>An apparatus is provided which comprises: a processor die; a processor substrate having a region extended away from the processor die, wherein the processor die is mounted on the processor substrate, wherein the extended region has at least one signal interface which is connectable to a top-side connector; and an interposer coupled to the processor substrate and a motherboard.</description><language>eng ; fre ; ger</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20190410&amp;DB=EPODOC&amp;CC=EP&amp;NR=3465753A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20190410&amp;DB=EPODOC&amp;CC=EP&amp;NR=3465753A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>AOKI, Russell S</creatorcontrib><creatorcontrib>THIBADO, Jonathan W</creatorcontrib><creatorcontrib>SMALLEY, Jeffory L</creatorcontrib><title>TOP-SIDE CONNECTOR INTERFACE FOR PROCESSOR PACKAGING</title><description>An apparatus is provided which comprises: a processor die; a processor substrate having a region extended away from the processor die, wherein the processor die is mounted on the processor substrate, wherein the extended region has at least one signal interface which is connectable to a top-side connector; and an interposer coupled to the processor substrate and a motherboard.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDAJ8Q_QDfZ0cVVw9vfzc3UO8Q9S8PQLcQ1yc3R2VXAD8gKC_J1dg4NBLEdnb0d3Tz93HgbWtMSc4lReKM3NoODmGuLsoZtakB-fWlyQmJyal1oS7xpgbGJmam5q7GhoTIQSAIGBJxI</recordid><startdate>20190410</startdate><enddate>20190410</enddate><creator>AOKI, Russell S</creator><creator>THIBADO, Jonathan W</creator><creator>SMALLEY, Jeffory L</creator><scope>EVB</scope></search><sort><creationdate>20190410</creationdate><title>TOP-SIDE CONNECTOR INTERFACE FOR PROCESSOR PACKAGING</title><author>AOKI, Russell S ; THIBADO, Jonathan W ; SMALLEY, Jeffory L</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP3465753A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre ; ger</language><creationdate>2019</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>AOKI, Russell S</creatorcontrib><creatorcontrib>THIBADO, Jonathan W</creatorcontrib><creatorcontrib>SMALLEY, Jeffory L</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>AOKI, Russell S</au><au>THIBADO, Jonathan W</au><au>SMALLEY, Jeffory L</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>TOP-SIDE CONNECTOR INTERFACE FOR PROCESSOR PACKAGING</title><date>2019-04-10</date><risdate>2019</risdate><abstract>An apparatus is provided which comprises: a processor die; a processor substrate having a region extended away from the processor die, wherein the processor die is mounted on the processor substrate, wherein the extended region has at least one signal interface which is connectable to a top-side connector; and an interposer coupled to the processor substrate and a motherboard.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng ; fre ; ger
recordid cdi_epo_espacenet_EP3465753A1
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title TOP-SIDE CONNECTOR INTERFACE FOR PROCESSOR PACKAGING
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-06T07%3A22%3A23IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=AOKI,%20Russell%20S&rft.date=2019-04-10&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EEP3465753A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true