SYSTEMS AND METHODS FOR USING ERROR CORRECTION AND PIPELINING TECHNIQUES FOR AN ACCESS TRIGGERED COMPUTER ARCHITECTURE

SYSTEMS AND METHODS FOR USING ERROR CORRECTION AND PIPELINING TECHNIQUES FOR AN ACCESS TRIGGERED COMPUTER ARCHITECTURE

A method for improving performance of an access triggered architecture for a computer implemented application is provided. The method first executes typical operations of the access triggered architecture according to an execution time, wherein the typical operations comprise: obtaining a dataset an...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: GILREATH, Jon Douglas, GAVAGAN IV, Vince J, KREIDER, Thom, WARNICA, Gary, KAMMANN, Paul D, STRONG, Ronald E
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator GILREATH, Jon Douglas
GAVAGAN IV, Vince J
KREIDER, Thom
WARNICA, Gary
KAMMANN, Paul D
STRONG, Ronald E
description A method for improving performance of an access triggered architecture for a computer implemented application is provided. The method first executes typical operations of the access triggered architecture according to an execution time, wherein the typical operations comprise: obtaining a dataset and an instruction set; and using the instruction set to transmit the dataset to a functional block associated with an operation, wherein the functional block performs the operation using the dataset to generate a revised dataset. The method further creates a pipeline of the typical operations to reduce the execution time of the typical operations, to create a reduced execution time; and executes the typical operations according to the reduced execution time, using the pipeline.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_EP3460654A3</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>EP3460654A3</sourcerecordid><originalsourceid>FETCH-epo_espacenet_EP3460654A33</originalsourceid><addsrcrecordid>eNqNi00KwjAQRrtxIeod5gKC0Np9SabNgE3iZLJwVYrElWih4vmNPwdw9X3w3lsWz3AKgn2AxmroUYzTAVrHEAPZDpA5f-WYUQk5-9E8eTyQfXNBZSwdI36jJgtKYQggTF2HjDrHvY-CGbIylAOJjOticRmvc9r8dlVAi6LMNk33Ic3TeE639BjQl1W9q_dVU5Z_KC_gyzlh</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SYSTEMS AND METHODS FOR USING ERROR CORRECTION AND PIPELINING TECHNIQUES FOR AN ACCESS TRIGGERED COMPUTER ARCHITECTURE</title><source>esp@cenet</source><creator>GILREATH, Jon Douglas ; GAVAGAN IV, Vince J ; KREIDER, Thom ; WARNICA, Gary ; KAMMANN, Paul D ; STRONG, Ronald E</creator><creatorcontrib>GILREATH, Jon Douglas ; GAVAGAN IV, Vince J ; KREIDER, Thom ; WARNICA, Gary ; KAMMANN, Paul D ; STRONG, Ronald E</creatorcontrib><description>A method for improving performance of an access triggered architecture for a computer implemented application is provided. The method first executes typical operations of the access triggered architecture according to an execution time, wherein the typical operations comprise: obtaining a dataset and an instruction set; and using the instruction set to transmit the dataset to a functional block associated with an operation, wherein the functional block performs the operation using the dataset to generate a revised dataset. The method further creates a pipeline of the typical operations to reduce the execution time of the typical operations, to create a reduced execution time; and executes the typical operations according to the reduced execution time, using the pipeline.</description><language>eng ; fre ; ger</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2019</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20190403&amp;DB=EPODOC&amp;CC=EP&amp;NR=3460654A3$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20190403&amp;DB=EPODOC&amp;CC=EP&amp;NR=3460654A3$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>GILREATH, Jon Douglas</creatorcontrib><creatorcontrib>GAVAGAN IV, Vince J</creatorcontrib><creatorcontrib>KREIDER, Thom</creatorcontrib><creatorcontrib>WARNICA, Gary</creatorcontrib><creatorcontrib>KAMMANN, Paul D</creatorcontrib><creatorcontrib>STRONG, Ronald E</creatorcontrib><title>SYSTEMS AND METHODS FOR USING ERROR CORRECTION AND PIPELINING TECHNIQUES FOR AN ACCESS TRIGGERED COMPUTER ARCHITECTURE</title><description>A method for improving performance of an access triggered architecture for a computer implemented application is provided. The method first executes typical operations of the access triggered architecture according to an execution time, wherein the typical operations comprise: obtaining a dataset and an instruction set; and using the instruction set to transmit the dataset to a functional block associated with an operation, wherein the functional block performs the operation using the dataset to generate a revised dataset. The method further creates a pipeline of the typical operations to reduce the execution time of the typical operations, to create a reduced execution time; and executes the typical operations according to the reduced execution time, using the pipeline.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2019</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNi00KwjAQRrtxIeod5gKC0Np9SabNgE3iZLJwVYrElWih4vmNPwdw9X3w3lsWz3AKgn2AxmroUYzTAVrHEAPZDpA5f-WYUQk5-9E8eTyQfXNBZSwdI36jJgtKYQggTF2HjDrHvY-CGbIylAOJjOticRmvc9r8dlVAi6LMNk33Ic3TeE639BjQl1W9q_dVU5Z_KC_gyzlh</recordid><startdate>20190403</startdate><enddate>20190403</enddate><creator>GILREATH, Jon Douglas</creator><creator>GAVAGAN IV, Vince J</creator><creator>KREIDER, Thom</creator><creator>WARNICA, Gary</creator><creator>KAMMANN, Paul D</creator><creator>STRONG, Ronald E</creator><scope>EVB</scope></search><sort><creationdate>20190403</creationdate><title>SYSTEMS AND METHODS FOR USING ERROR CORRECTION AND PIPELINING TECHNIQUES FOR AN ACCESS TRIGGERED COMPUTER ARCHITECTURE</title><author>GILREATH, Jon Douglas ; GAVAGAN IV, Vince J ; KREIDER, Thom ; WARNICA, Gary ; KAMMANN, Paul D ; STRONG, Ronald E</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP3460654A33</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre ; ger</language><creationdate>2019</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>GILREATH, Jon Douglas</creatorcontrib><creatorcontrib>GAVAGAN IV, Vince J</creatorcontrib><creatorcontrib>KREIDER, Thom</creatorcontrib><creatorcontrib>WARNICA, Gary</creatorcontrib><creatorcontrib>KAMMANN, Paul D</creatorcontrib><creatorcontrib>STRONG, Ronald E</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>GILREATH, Jon Douglas</au><au>GAVAGAN IV, Vince J</au><au>KREIDER, Thom</au><au>WARNICA, Gary</au><au>KAMMANN, Paul D</au><au>STRONG, Ronald E</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SYSTEMS AND METHODS FOR USING ERROR CORRECTION AND PIPELINING TECHNIQUES FOR AN ACCESS TRIGGERED COMPUTER ARCHITECTURE</title><date>2019-04-03</date><risdate>2019</risdate><abstract>A method for improving performance of an access triggered architecture for a computer implemented application is provided. The method first executes typical operations of the access triggered architecture according to an execution time, wherein the typical operations comprise: obtaining a dataset and an instruction set; and using the instruction set to transmit the dataset to a functional block associated with an operation, wherein the functional block performs the operation using the dataset to generate a revised dataset. The method further creates a pipeline of the typical operations to reduce the execution time of the typical operations, to create a reduced execution time; and executes the typical operations according to the reduced execution time, using the pipeline.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng ; fre ; ger
recordid cdi_epo_espacenet_EP3460654A3
source esp@cenet
subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title SYSTEMS AND METHODS FOR USING ERROR CORRECTION AND PIPELINING TECHNIQUES FOR AN ACCESS TRIGGERED COMPUTER ARCHITECTURE
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-05T19%3A27%3A42IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=GILREATH,%20Jon%20Douglas&rft.date=2019-04-03&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EEP3460654A3%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true