A COMPUTER ARCHITECTURE WITH A HARDWARE ACCUMULATOR RESET

A COMPUTER ARCHITECTURE WITH A HARDWARE ACCUMULATOR RESET

A processor is provided with an accumulator. An event is selected to produce one or more selected events. A reset signal to the accumulator is generated responsive to the selected event. Responsive to the reset signal, the accumulator is reset to zero or another initial value while avoiding breaking...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Arbeli, Yosi, Dogon, Gil Israel, Kreinin, Yosef
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:A processor is provided with an accumulator. An event is selected to produce one or more selected events. A reset signal to the accumulator is generated responsive to the selected event. Responsive to the reset signal, the accumulator is reset to zero or another initial value while avoiding breaking pipelined execution of the processor.