PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS
A microelectronic package comprising: a substrate (12) having first (18) and second (20) regions, the substrate having a first surface (14) and a remote second surface (16) ; at least one microelectronic element (22) overlying the first surface within the first region; electrically conductive elemen...
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| creator | WANG, Wei-shun CO, Reynaldo YANG, Se Young ZHAO, Zhijun ALATORRE, Roseann CHAU, Ellis DAMBERG, Philip |
| description | A microelectronic package comprising:
a substrate (12) having first (18) and second (20) regions, the substrate having a first surface (14) and a remote second surface (16) ;
at least one microelectronic element (22) overlying the first surface within the first region;
electrically conductive elements (28) exposed at at least one of the first surface and the second surface of the substrate within the second region, at least some of the conductive elements being electrically connected to the at least one microelectronic element;
wire bonds (32,732B), each defining a base (34) joined to a respective one of the conductive elements, and each wire bond having a second portion (736) extending away from the respective base and relative to the at least one surface of the substrate at an angle between 25° and 90°, the wire bonds further having ends (36,738B) remote from the substrate and remote from the bases, wherein the end of at least one (738B) of the wire bonds is defined on a tip that is tapered in at least one direction extending beyond a cylindrical portion (736) of the at least one of the wire bonds, the tip having a centroid (740) that is offset in a radial direction (741) from an axis (742) of the cylindrical portion; and
a dielectric encapsulation layer (42) extending from at least one of the first or second surfaces and covering portions of the wire bonds, wherein unencapsulated portions (38, 738B) of the wire include the ends. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_EP3416190A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>EP3416190A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_EP3416190A13</originalsourceid><addsrcrecordid>eNrjZNAPcHT2dnR31fX304UyFRyDg119nXwiFcI9QzyARJCrgpO_n4tCmKdjMA8Da1piTnEqL5TmZlBwcw1x9tBNLciPTy0uSExOzUstiXcNMDYxNDO0NHA0NCZCCQCb2SVG</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS</title><source>esp@cenet</source><creator>WANG, Wei-shun ; CO, Reynaldo ; YANG, Se Young ; ZHAO, Zhijun ; ALATORRE, Roseann ; CHAU, Ellis ; DAMBERG, Philip</creator><creatorcontrib>WANG, Wei-shun ; CO, Reynaldo ; YANG, Se Young ; ZHAO, Zhijun ; ALATORRE, Roseann ; CHAU, Ellis ; DAMBERG, Philip</creatorcontrib><description>A microelectronic package comprising:
a substrate (12) having first (18) and second (20) regions, the substrate having a first surface (14) and a remote second surface (16) ;
at least one microelectronic element (22) overlying the first surface within the first region;
electrically conductive elements (28) exposed at at least one of the first surface and the second surface of the substrate within the second region, at least some of the conductive elements being electrically connected to the at least one microelectronic element;
wire bonds (32,732B), each defining a base (34) joined to a respective one of the conductive elements, and each wire bond having a second portion (736) extending away from the respective base and relative to the at least one surface of the substrate at an angle between 25° and 90°, the wire bonds further having ends (36,738B) remote from the substrate and remote from the bases, wherein the end of at least one (738B) of the wire bonds is defined on a tip that is tapered in at least one direction extending beyond a cylindrical portion (736) of the at least one of the wire bonds, the tip having a centroid (740) that is offset in a radial direction (741) from an axis (742) of the cylindrical portion; and
a dielectric encapsulation layer (42) extending from at least one of the first or second surfaces and covering portions of the wire bonds, wherein unencapsulated portions (38, 738B) of the wire include the ends.</description><language>eng ; fre ; ger</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2018</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20181219&DB=EPODOC&CC=EP&NR=3416190A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20181219&DB=EPODOC&CC=EP&NR=3416190A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>WANG, Wei-shun</creatorcontrib><creatorcontrib>CO, Reynaldo</creatorcontrib><creatorcontrib>YANG, Se Young</creatorcontrib><creatorcontrib>ZHAO, Zhijun</creatorcontrib><creatorcontrib>ALATORRE, Roseann</creatorcontrib><creatorcontrib>CHAU, Ellis</creatorcontrib><creatorcontrib>DAMBERG, Philip</creatorcontrib><title>PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS</title><description>A microelectronic package comprising:
a substrate (12) having first (18) and second (20) regions, the substrate having a first surface (14) and a remote second surface (16) ;
at least one microelectronic element (22) overlying the first surface within the first region;
electrically conductive elements (28) exposed at at least one of the first surface and the second surface of the substrate within the second region, at least some of the conductive elements being electrically connected to the at least one microelectronic element;
wire bonds (32,732B), each defining a base (34) joined to a respective one of the conductive elements, and each wire bond having a second portion (736) extending away from the respective base and relative to the at least one surface of the substrate at an angle between 25° and 90°, the wire bonds further having ends (36,738B) remote from the substrate and remote from the bases, wherein the end of at least one (738B) of the wire bonds is defined on a tip that is tapered in at least one direction extending beyond a cylindrical portion (736) of the at least one of the wire bonds, the tip having a centroid (740) that is offset in a radial direction (741) from an axis (742) of the cylindrical portion; and
a dielectric encapsulation layer (42) extending from at least one of the first or second surfaces and covering portions of the wire bonds, wherein unencapsulated portions (38, 738B) of the wire include the ends.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2018</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNAPcHT2dnR31fX304UyFRyDg119nXwiFcI9QzyARJCrgpO_n4tCmKdjMA8Da1piTnEqL5TmZlBwcw1x9tBNLciPTy0uSExOzUstiXcNMDYxNDO0NHA0NCZCCQCb2SVG</recordid><startdate>20181219</startdate><enddate>20181219</enddate><creator>WANG, Wei-shun</creator><creator>CO, Reynaldo</creator><creator>YANG, Se Young</creator><creator>ZHAO, Zhijun</creator><creator>ALATORRE, Roseann</creator><creator>CHAU, Ellis</creator><creator>DAMBERG, Philip</creator><scope>EVB</scope></search><sort><creationdate>20181219</creationdate><title>PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS</title><author>WANG, Wei-shun ; CO, Reynaldo ; YANG, Se Young ; ZHAO, Zhijun ; ALATORRE, Roseann ; CHAU, Ellis ; DAMBERG, Philip</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP3416190A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre ; ger</language><creationdate>2018</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>WANG, Wei-shun</creatorcontrib><creatorcontrib>CO, Reynaldo</creatorcontrib><creatorcontrib>YANG, Se Young</creatorcontrib><creatorcontrib>ZHAO, Zhijun</creatorcontrib><creatorcontrib>ALATORRE, Roseann</creatorcontrib><creatorcontrib>CHAU, Ellis</creatorcontrib><creatorcontrib>DAMBERG, Philip</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>WANG, Wei-shun</au><au>CO, Reynaldo</au><au>YANG, Se Young</au><au>ZHAO, Zhijun</au><au>ALATORRE, Roseann</au><au>CHAU, Ellis</au><au>DAMBERG, Philip</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS</title><date>2018-12-19</date><risdate>2018</risdate><abstract>A microelectronic package comprising:
a substrate (12) having first (18) and second (20) regions, the substrate having a first surface (14) and a remote second surface (16) ;
at least one microelectronic element (22) overlying the first surface within the first region;
electrically conductive elements (28) exposed at at least one of the first surface and the second surface of the substrate within the second region, at least some of the conductive elements being electrically connected to the at least one microelectronic element;
wire bonds (32,732B), each defining a base (34) joined to a respective one of the conductive elements, and each wire bond having a second portion (736) extending away from the respective base and relative to the at least one surface of the substrate at an angle between 25° and 90°, the wire bonds further having ends (36,738B) remote from the substrate and remote from the bases, wherein the end of at least one (738B) of the wire bonds is defined on a tip that is tapered in at least one direction extending beyond a cylindrical portion (736) of the at least one of the wire bonds, the tip having a centroid (740) that is offset in a radial direction (741) from an axis (742) of the cylindrical portion; and
a dielectric encapsulation layer (42) extending from at least one of the first or second surfaces and covering portions of the wire bonds, wherein unencapsulated portions (38, 738B) of the wire include the ends.</abstract><oa>free_for_read</oa></addata></record> |
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| language | eng ; fre ; ger |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS |
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