MEASURING ADDRESS TRANSLATION LATENCY

An apparatus includes processing circuitry to process instructions, some of which may require addresses to be translated. The apparatus also includes address translation circuitry to translate addresses in response to instruction processed by the processing circuitry. Furthermore, the apparatus also...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	WILLIAMS, Michael John, FILIPPO, Michael, SHAFI, Hazim
Format:	Patent
Sprache:	eng ; fre ; ger
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!