INSTRUCTION AND LOGIC FOR CACHE CONTROL OPERATIONS
In one embodiment, a processor includes: a fetch logic to fetch instructions; a decode logic to decode the instructions; a cache memory; and a control logic to receive a cache filter instruction and responsive to the cache filter instruction enable only a selected portion of a memory address space t...
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| creator | SASANKA, Ruchira |
| description | In one embodiment, a processor includes: a fetch logic to fetch instructions; a decode logic to decode the instructions; a cache memory; and a control logic to receive a cache filter instruction and responsive to the cache filter instruction enable only a selected portion of a memory address space to be eligible to be cached in the cache memory. The cache filter instruction may indicate the selected portion of the memory address space. Other embodiments are described and claimed. |
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| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_EP3380943A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>EP3380943A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_EP3380943A13</originalsourceid><addsrcrecordid>eNrjZDDy9AsOCQp1DvH091Nw9HNR8PF393RWcPMPUnB2dPZwVXD29wsJ8vdR8A9wDXIEqQrmYWBNS8wpTuWF0twMCm6uIc4euqkF-fGpxQWJyal5qSXxrgHGxhYGlibGjobGRCgBADQ0JoA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>INSTRUCTION AND LOGIC FOR CACHE CONTROL OPERATIONS</title><source>esp@cenet</source><creator>SASANKA, Ruchira</creator><creatorcontrib>SASANKA, Ruchira</creatorcontrib><description>In one embodiment, a processor includes: a fetch logic to fetch instructions; a decode logic to decode the instructions; a cache memory; and a control logic to receive a cache filter instruction and responsive to the cache filter instruction enable only a selected portion of a memory address space to be eligible to be cached in the cache memory. The cache filter instruction may indicate the selected portion of the memory address space. Other embodiments are described and claimed.</description><language>eng ; fre ; ger</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2018</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20181003&DB=EPODOC&CC=EP&NR=3380943A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76318</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20181003&DB=EPODOC&CC=EP&NR=3380943A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>SASANKA, Ruchira</creatorcontrib><title>INSTRUCTION AND LOGIC FOR CACHE CONTROL OPERATIONS</title><description>In one embodiment, a processor includes: a fetch logic to fetch instructions; a decode logic to decode the instructions; a cache memory; and a control logic to receive a cache filter instruction and responsive to the cache filter instruction enable only a selected portion of a memory address space to be eligible to be cached in the cache memory. The cache filter instruction may indicate the selected portion of the memory address space. Other embodiments are described and claimed.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2018</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDDy9AsOCQp1DvH091Nw9HNR8PF393RWcPMPUnB2dPZwVXD29wsJ8vdR8A9wDXIEqQrmYWBNS8wpTuWF0twMCm6uIc4euqkF-fGpxQWJyal5qSXxrgHGxhYGlibGjobGRCgBADQ0JoA</recordid><startdate>20181003</startdate><enddate>20181003</enddate><creator>SASANKA, Ruchira</creator><scope>EVB</scope></search><sort><creationdate>20181003</creationdate><title>INSTRUCTION AND LOGIC FOR CACHE CONTROL OPERATIONS</title><author>SASANKA, Ruchira</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP3380943A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre ; ger</language><creationdate>2018</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>SASANKA, Ruchira</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>SASANKA, Ruchira</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>INSTRUCTION AND LOGIC FOR CACHE CONTROL OPERATIONS</title><date>2018-10-03</date><risdate>2018</risdate><abstract>In one embodiment, a processor includes: a fetch logic to fetch instructions; a decode logic to decode the instructions; a cache memory; and a control logic to receive a cache filter instruction and responsive to the cache filter instruction enable only a selected portion of a memory address space to be eligible to be cached in the cache memory. The cache filter instruction may indicate the selected portion of the memory address space. Other embodiments are described and claimed.</abstract><oa>free_for_read</oa></addata></record> |
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| language | eng ; fre ; ger |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | INSTRUCTION AND LOGIC FOR CACHE CONTROL OPERATIONS |
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