FSK DECODING USING ENVELOP COMPARISON IN THE DIGITAL DOMAIN

A method of FSK decoding includes generating a pulse waveform (R'Edge) from a received FSK encoded signal (FSK signal) and a system clock (Sys_clk). From R'Edge and Sys_clk clocks are generated including a first clock and second clock framing a logic '0' level of the FSK signal,...

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Hauptverfasser: PAI, Sandeep, KN, Dinesh Kumar, GUDI, Balakrishna G, SATHYANARAYANA, Aravind
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creator PAI, Sandeep
KN, Dinesh Kumar
GUDI, Balakrishna G
SATHYANARAYANA, Aravind
description A method of FSK decoding includes generating a pulse waveform (R'Edge) from a received FSK encoded signal (FSK signal) and a system clock (Sys_clk). From R'Edge and Sys_clk clocks are generated including a first clock and second clock framing a logic '0' level of the FSK signal, and a third clock and fourth clock framing a logic '1' level of the FSK signal. At least four frequency envelopes are generated from the clocks including a logic '0' envelope, a logic '1' envelope, a lower frequency envelope below the logic '0' envelope, and an upper frequency envelope above the logic '1' envelope. R'Edge is compared to the four envelopes, and a decoded output is produced, logic '0' if the R'Edge overlaps the logic '0' envelope, logic '1' if R'Edge overlaps the logic '1' envelope, and a previous output state if R'Edge does not overlap the logic '0' or logic '1' envelope.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_EP3329646B1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>EP3329646B1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_EP3329646B13</originalsourceid><addsrcrecordid>eNrjZLB2C_ZWcHF19nfx9HNXCA0Gka5-Ya4-_gEKzv6-AY5BnsH-fgqefgohHq4KLp7uniGOPgou_r6Onn48DKxpiTnFqbxQmptBwc01xNlDN7UgPz61uCAxOTUvtSTeNcDY2MjSzMTMydCYCCUAdNQotw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>FSK DECODING USING ENVELOP COMPARISON IN THE DIGITAL DOMAIN</title><source>esp@cenet</source><creator>PAI, Sandeep ; KN, Dinesh Kumar ; GUDI, Balakrishna G ; SATHYANARAYANA, Aravind</creator><creatorcontrib>PAI, Sandeep ; KN, Dinesh Kumar ; GUDI, Balakrishna G ; SATHYANARAYANA, Aravind</creatorcontrib><description>A method of FSK decoding includes generating a pulse waveform (R'Edge) from a received FSK encoded signal (FSK signal) and a system clock (Sys_clk). From R'Edge and Sys_clk clocks are generated including a first clock and second clock framing a logic '0' level of the FSK signal, and a third clock and fourth clock framing a logic '1' level of the FSK signal. At least four frequency envelopes are generated from the clocks including a logic '0' envelope, a logic '1' envelope, a lower frequency envelope below the logic '0' envelope, and an upper frequency envelope above the logic '1' envelope. R'Edge is compared to the four envelopes, and a decoded output is produced, logic '0' if the R'Edge overlaps the logic '0' envelope, logic '1' if R'Edge overlaps the logic '1' envelope, and a previous output state if R'Edge does not overlap the logic '0' or logic '1' envelope.</description><language>eng ; fre ; ger</language><subject>BASIC ELECTRONIC CIRCUITRY ; DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TOANOTHER ; ELECTRIC COMMUNICATION TECHNIQUE ; ELECTRICITY ; TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><creationdate>2020</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20200617&amp;DB=EPODOC&amp;CC=EP&amp;NR=3329646B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,777,882,25545,76296</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20200617&amp;DB=EPODOC&amp;CC=EP&amp;NR=3329646B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>PAI, Sandeep</creatorcontrib><creatorcontrib>KN, Dinesh Kumar</creatorcontrib><creatorcontrib>GUDI, Balakrishna G</creatorcontrib><creatorcontrib>SATHYANARAYANA, Aravind</creatorcontrib><title>FSK DECODING USING ENVELOP COMPARISON IN THE DIGITAL DOMAIN</title><description>A method of FSK decoding includes generating a pulse waveform (R'Edge) from a received FSK encoded signal (FSK signal) and a system clock (Sys_clk). From R'Edge and Sys_clk clocks are generated including a first clock and second clock framing a logic '0' level of the FSK signal, and a third clock and fourth clock framing a logic '1' level of the FSK signal. At least four frequency envelopes are generated from the clocks including a logic '0' envelope, a logic '1' envelope, a lower frequency envelope below the logic '0' envelope, and an upper frequency envelope above the logic '1' envelope. R'Edge is compared to the four envelopes, and a decoded output is produced, logic '0' if the R'Edge overlaps the logic '0' envelope, logic '1' if R'Edge overlaps the logic '1' envelope, and a previous output state if R'Edge does not overlap the logic '0' or logic '1' envelope.</description><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TOANOTHER</subject><subject>ELECTRIC COMMUNICATION TECHNIQUE</subject><subject>ELECTRICITY</subject><subject>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2020</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLB2C_ZWcHF19nfx9HNXCA0Gka5-Ya4-_gEKzv6-AY5BnsH-fgqefgohHq4KLp7uniGOPgou_r6Onn48DKxpiTnFqbxQmptBwc01xNlDN7UgPz61uCAxOTUvtSTeNcDY2MjSzMTMydCYCCUAdNQotw</recordid><startdate>20200617</startdate><enddate>20200617</enddate><creator>PAI, Sandeep</creator><creator>KN, Dinesh Kumar</creator><creator>GUDI, Balakrishna G</creator><creator>SATHYANARAYANA, Aravind</creator><scope>EVB</scope></search><sort><creationdate>20200617</creationdate><title>FSK DECODING USING ENVELOP COMPARISON IN THE DIGITAL DOMAIN</title><author>PAI, Sandeep ; KN, Dinesh Kumar ; GUDI, Balakrishna G ; SATHYANARAYANA, Aravind</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP3329646B13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre ; ger</language><creationdate>2020</creationdate><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TOANOTHER</topic><topic>ELECTRIC COMMUNICATION TECHNIQUE</topic><topic>ELECTRICITY</topic><topic>TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION</topic><toplevel>online_resources</toplevel><creatorcontrib>PAI, Sandeep</creatorcontrib><creatorcontrib>KN, Dinesh Kumar</creatorcontrib><creatorcontrib>GUDI, Balakrishna G</creatorcontrib><creatorcontrib>SATHYANARAYANA, Aravind</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>PAI, Sandeep</au><au>KN, Dinesh Kumar</au><au>GUDI, Balakrishna G</au><au>SATHYANARAYANA, Aravind</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>FSK DECODING USING ENVELOP COMPARISON IN THE DIGITAL DOMAIN</title><date>2020-06-17</date><risdate>2020</risdate><abstract>A method of FSK decoding includes generating a pulse waveform (R'Edge) from a received FSK encoded signal (FSK signal) and a system clock (Sys_clk). From R'Edge and Sys_clk clocks are generated including a first clock and second clock framing a logic '0' level of the FSK signal, and a third clock and fourth clock framing a logic '1' level of the FSK signal. At least four frequency envelopes are generated from the clocks including a logic '0' envelope, a logic '1' envelope, a lower frequency envelope below the logic '0' envelope, and an upper frequency envelope above the logic '1' envelope. R'Edge is compared to the four envelopes, and a decoded output is produced, logic '0' if the R'Edge overlaps the logic '0' envelope, logic '1' if R'Edge overlaps the logic '1' envelope, and a previous output state if R'Edge does not overlap the logic '0' or logic '1' envelope.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRONIC CIRCUITRY
DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TOANOTHER
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
title FSK DECODING USING ENVELOP COMPARISON IN THE DIGITAL DOMAIN
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-20T14%3A58%3A11IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=PAI,%20Sandeep&rft.date=2020-06-17&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EEP3329646B1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true