VISUALIZATION OF ANALYSIS PROCESS PARAMETERS FOR LAYOUT-BASED CHECKS

VISUALIZATION OF ANALYSIS PROCESS PARAMETERS FOR LAYOUT-BASED CHECKS

Techniques and mechanisms for marking the parameters of a circuit analysis process for visual identification are disclosed. The visually-identified parameters can then be employed with the results of the circuit analysis to debug the layout design.

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Bibliographische Detailangaben
Hauptverfasser: GIBSON, Patrick, D, KHARAS, Farhad, T, CHANG, I-Shan, JACKSON III, MacDonald, Hall
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:Techniques and mechanisms for marking the parameters of a circuit analysis process for visual identification are disclosed. The visually-identified parameters can then be employed with the results of the circuit analysis to debug the layout design.