APPARATUS AND METHOD FOR INTER-STRAND COMMUNICATION

A processor includes execution units, a front end, and an execution engine. The front end includes logic to receive instructions in different strands of ordered instructions and to send the instructions to the execution engine. The engine includes logic to determine that the instructions in differen...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: SHISHLOV, Sergey, BUROV, Valentin, MASLENNIKOV, Dmitry, TITOV, Alexandr, MATVEYEV, Pavel
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator SHISHLOV, Sergey
BUROV, Valentin
MASLENNIKOV, Dmitry
TITOV, Alexandr
MATVEYEV, Pavel
description A processor includes execution units, a front end, and an execution engine. The front end includes logic to receive instructions in different strands of ordered instructions and to send the instructions to the execution engine. The engine includes logic to determine that the instructions in different strands reference a same logical register mapped to a physical register, that the instructions reference each other, and that one of the instructions referencing the other was processed after the instruction defining the logical register.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_EP3274815A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>EP3274815A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_EP3274815A13</originalsourceid><addsrcrecordid>eNrjZDB2DAhwDHIMCQ1WcPRzUfB1DfHwd1Fw8w9S8PQLcQ3SDQ4JAok7-_v6hvp5OjuGePr78TCwpiXmFKfyQmluBgU31xBnD93Ugvz41OKCxOTUvNSSeNcAYyNzEwtDU0dDYyKUAABgGybb</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>APPARATUS AND METHOD FOR INTER-STRAND COMMUNICATION</title><source>esp@cenet</source><creator>SHISHLOV, Sergey ; BUROV, Valentin ; MASLENNIKOV, Dmitry ; TITOV, Alexandr ; MATVEYEV, Pavel</creator><creatorcontrib>SHISHLOV, Sergey ; BUROV, Valentin ; MASLENNIKOV, Dmitry ; TITOV, Alexandr ; MATVEYEV, Pavel</creatorcontrib><description>A processor includes execution units, a front end, and an execution engine. The front end includes logic to receive instructions in different strands of ordered instructions and to send the instructions to the execution engine. The engine includes logic to determine that the instructions in different strands reference a same logical register mapped to a physical register, that the instructions reference each other, and that one of the instructions referencing the other was processed after the instruction defining the logical register.</description><language>eng ; fre ; ger</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2018</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20180131&amp;DB=EPODOC&amp;CC=EP&amp;NR=3274815A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20180131&amp;DB=EPODOC&amp;CC=EP&amp;NR=3274815A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>SHISHLOV, Sergey</creatorcontrib><creatorcontrib>BUROV, Valentin</creatorcontrib><creatorcontrib>MASLENNIKOV, Dmitry</creatorcontrib><creatorcontrib>TITOV, Alexandr</creatorcontrib><creatorcontrib>MATVEYEV, Pavel</creatorcontrib><title>APPARATUS AND METHOD FOR INTER-STRAND COMMUNICATION</title><description>A processor includes execution units, a front end, and an execution engine. The front end includes logic to receive instructions in different strands of ordered instructions and to send the instructions to the execution engine. The engine includes logic to determine that the instructions in different strands reference a same logical register mapped to a physical register, that the instructions reference each other, and that one of the instructions referencing the other was processed after the instruction defining the logical register.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2018</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDB2DAhwDHIMCQ1WcPRzUfB1DfHwd1Fw8w9S8PQLcQ3SDQ4JAok7-_v6hvp5OjuGePr78TCwpiXmFKfyQmluBgU31xBnD93Ugvz41OKCxOTUvNSSeNcAYyNzEwtDU0dDYyKUAABgGybb</recordid><startdate>20180131</startdate><enddate>20180131</enddate><creator>SHISHLOV, Sergey</creator><creator>BUROV, Valentin</creator><creator>MASLENNIKOV, Dmitry</creator><creator>TITOV, Alexandr</creator><creator>MATVEYEV, Pavel</creator><scope>EVB</scope></search><sort><creationdate>20180131</creationdate><title>APPARATUS AND METHOD FOR INTER-STRAND COMMUNICATION</title><author>SHISHLOV, Sergey ; BUROV, Valentin ; MASLENNIKOV, Dmitry ; TITOV, Alexandr ; MATVEYEV, Pavel</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP3274815A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre ; ger</language><creationdate>2018</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>SHISHLOV, Sergey</creatorcontrib><creatorcontrib>BUROV, Valentin</creatorcontrib><creatorcontrib>MASLENNIKOV, Dmitry</creatorcontrib><creatorcontrib>TITOV, Alexandr</creatorcontrib><creatorcontrib>MATVEYEV, Pavel</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>SHISHLOV, Sergey</au><au>BUROV, Valentin</au><au>MASLENNIKOV, Dmitry</au><au>TITOV, Alexandr</au><au>MATVEYEV, Pavel</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>APPARATUS AND METHOD FOR INTER-STRAND COMMUNICATION</title><date>2018-01-31</date><risdate>2018</risdate><abstract>A processor includes execution units, a front end, and an execution engine. The front end includes logic to receive instructions in different strands of ordered instructions and to send the instructions to the execution engine. The engine includes logic to determine that the instructions in different strands reference a same logical register mapped to a physical register, that the instructions reference each other, and that one of the instructions referencing the other was processed after the instruction defining the logical register.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng ; fre ; ger
recordid cdi_epo_espacenet_EP3274815A1
source esp@cenet
subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title APPARATUS AND METHOD FOR INTER-STRAND COMMUNICATION
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-07T15%3A01%3A52IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=SHISHLOV,%20Sergey&rft.date=2018-01-31&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EEP3274815A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true