TRANSISTORS CONFIGURED FOR GATE OVERBIASING AND CIRCUITS THEREFROM

TRANSISTORS CONFIGURED FOR GATE OVERBIASING AND CIRCUITS THEREFROM

An electronic circuit and methods of operating the electronic circuit are provided. The electronic circuit includes a pull-up transistor for pulling up an input/output (I/O) node of the output circuit to a first voltage and a first isolation transistor for coupling the pull-up transistor to the I/O...

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Hauptverfasser: ISAKANIAN, Patrick, YU, Bo, THILENIUS, Stephen Clifford, JALILIZEINALI, Reza, LOKE, Alvin Leng Sun
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
PULSE TECHNIQUE
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creator ISAKANIAN, Patrick
YU, Bo
THILENIUS, Stephen Clifford
JALILIZEINALI, Reza
LOKE, Alvin Leng Sun
description An electronic circuit and methods of operating the electronic circuit are provided. The electronic circuit includes a pull-up transistor for pulling up an input/output (I/O) node of the output circuit to a first voltage and a first isolation transistor for coupling the pull-up transistor to the I/O node. The electronic circuit also includes a pull-down transistor for pulling down the I/O node to a second voltage and a second isolation transistor for coupling the pull-down transistor to the I/O node. In the electronic circuit, the pull-up and the pull-down transistors are transistors supporting a first drain-to-source voltage and a first gate-to-source voltage, while the first and the second isolation transistors are transistors supporting the first drain-to-source voltage and a second gate-to-source voltage greater than the first gate-to-source voltage.
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subjects BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
PULSE TECHNIQUE
title TRANSISTORS CONFIGURED FOR GATE OVERBIASING AND CIRCUITS THEREFROM
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