STRUCTURE AND METHOD FOR MEMORY CELL ARRAY

STRUCTURE AND METHOD FOR MEMORY CELL ARRAY

A memory cell array structure includes memory cells (11) arranged in m rows and n columns on a substrate, and n columns of first (102) and second (103) well regions with different conductivity types alternatively arranged along the column direction. Each of the memory cells includes first (11a) and...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: CHIU, Shengfen, CAO, Heng
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:A memory cell array structure includes memory cells (11) arranged in m rows and n columns on a substrate, and n columns of first (102) and second (103) well regions with different conductivity types alternatively arranged along the column direction. Each of the memory cells includes first (11a) and second (11b) diodes. The first diode formed of a first doped region in the same column is disposed in the first well region. The second diode formed of a second doped region in the same column is disposed in the second well region. A third doped region (108) having the conductivity type of the first well region is disposed in the first well region and is connected to the reset line of the same column. A fourth doped region (109) having the conductivity type of the second well region is disposed in the second well region and is connected to the bit line of the same column.