CLOCK-GATING CELL WITH LOW AREA, LOW POWER, AND LOW SETUP TIME
A CGC includes an enable module and a latch module. The enable module has an enable module input and an enable module output. The latch module has latch module inputs and a latch module output. The latch module inputs include a latch module clock input for receiving a clock and a latch module enable...
Gespeichert in:
Hauptverfasser: | , , |
---|---|
Format: | Patent |
Sprache: | eng ; fre ; ger |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | DILLEN, Steven James RASOULI, Seid Hadi DATTA, Animesh |
description | A CGC includes an enable module and a latch module. The enable module has an enable module input and an enable module output. The latch module has latch module inputs and a latch module output. The latch module inputs include a latch module clock input for receiving a clock and a latch module enable input for receiving the enable module output. The latch module enable input is coupled to the enable module output. The latch module is configured to enable and to disable the clock via the latch module output based on the enable module input. The latch module includes an internal enable node that is the latch module output. The latch module is configured to cause the internal enable node to transition from low to high as a function of the enable module output and ĒC, where E is the internal enable node and C is the clock. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_EP3245735B1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>EP3245735B1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_EP3245735B13</originalsourceid><addsrcrecordid>eNrjZLBz9vF39tZ1dwzx9HNXcHb18VEI9wzxUPDxD1dwDHJ11AGzAvzDXYN0FBz9XMDcYNeQ0ACFEE9fVx4G1rTEnOJUXijNzaDg5hri7KGbWpAfn1pckJicmpdaEu8aYGxkYmpubOpkaEyEEgC-sikf</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>CLOCK-GATING CELL WITH LOW AREA, LOW POWER, AND LOW SETUP TIME</title><source>esp@cenet</source><creator>DILLEN, Steven James ; RASOULI, Seid Hadi ; DATTA, Animesh</creator><creatorcontrib>DILLEN, Steven James ; RASOULI, Seid Hadi ; DATTA, Animesh</creatorcontrib><description>A CGC includes an enable module and a latch module. The enable module has an enable module input and an enable module output. The latch module has latch module inputs and a latch module output. The latch module inputs include a latch module clock input for receiving a clock and a latch module enable input for receiving the enable module output. The latch module enable input is coupled to the enable module output. The latch module is configured to enable and to disable the clock via the latch module output based on the enable module input. The latch module includes an internal enable node that is the latch module output. The latch module is configured to cause the internal enable node to transition from low to high as a function of the enable module output and ĒC, where E is the internal enable node and C is the clock.</description><language>eng ; fre ; ger</language><subject>BASIC ELECTRONIC CIRCUITRY ; ELECTRICITY ; PULSE TECHNIQUE</subject><creationdate>2020</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20200805&DB=EPODOC&CC=EP&NR=3245735B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76318</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20200805&DB=EPODOC&CC=EP&NR=3245735B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>DILLEN, Steven James</creatorcontrib><creatorcontrib>RASOULI, Seid Hadi</creatorcontrib><creatorcontrib>DATTA, Animesh</creatorcontrib><title>CLOCK-GATING CELL WITH LOW AREA, LOW POWER, AND LOW SETUP TIME</title><description>A CGC includes an enable module and a latch module. The enable module has an enable module input and an enable module output. The latch module has latch module inputs and a latch module output. The latch module inputs include a latch module clock input for receiving a clock and a latch module enable input for receiving the enable module output. The latch module enable input is coupled to the enable module output. The latch module is configured to enable and to disable the clock via the latch module output based on the enable module input. The latch module includes an internal enable node that is the latch module output. The latch module is configured to cause the internal enable node to transition from low to high as a function of the enable module output and ĒC, where E is the internal enable node and C is the clock.</description><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>ELECTRICITY</subject><subject>PULSE TECHNIQUE</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2020</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLBz9vF39tZ1dwzx9HNXcHb18VEI9wzxUPDxD1dwDHJ11AGzAvzDXYN0FBz9XMDcYNeQ0ACFEE9fVx4G1rTEnOJUXijNzaDg5hri7KGbWpAfn1pckJicmpdaEu8aYGxkYmpubOpkaEyEEgC-sikf</recordid><startdate>20200805</startdate><enddate>20200805</enddate><creator>DILLEN, Steven James</creator><creator>RASOULI, Seid Hadi</creator><creator>DATTA, Animesh</creator><scope>EVB</scope></search><sort><creationdate>20200805</creationdate><title>CLOCK-GATING CELL WITH LOW AREA, LOW POWER, AND LOW SETUP TIME</title><author>DILLEN, Steven James ; RASOULI, Seid Hadi ; DATTA, Animesh</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP3245735B13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre ; ger</language><creationdate>2020</creationdate><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>ELECTRICITY</topic><topic>PULSE TECHNIQUE</topic><toplevel>online_resources</toplevel><creatorcontrib>DILLEN, Steven James</creatorcontrib><creatorcontrib>RASOULI, Seid Hadi</creatorcontrib><creatorcontrib>DATTA, Animesh</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>DILLEN, Steven James</au><au>RASOULI, Seid Hadi</au><au>DATTA, Animesh</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>CLOCK-GATING CELL WITH LOW AREA, LOW POWER, AND LOW SETUP TIME</title><date>2020-08-05</date><risdate>2020</risdate><abstract>A CGC includes an enable module and a latch module. The enable module has an enable module input and an enable module output. The latch module has latch module inputs and a latch module output. The latch module inputs include a latch module clock input for receiving a clock and a latch module enable input for receiving the enable module output. The latch module enable input is coupled to the enable module output. The latch module is configured to enable and to disable the clock via the latch module output based on the enable module input. The latch module includes an internal enable node that is the latch module output. The latch module is configured to cause the internal enable node to transition from low to high as a function of the enable module output and ĒC, where E is the internal enable node and C is the clock.</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng ; fre ; ger |
recordid | cdi_epo_espacenet_EP3245735B1 |
source | esp@cenet |
subjects | BASIC ELECTRONIC CIRCUITRY ELECTRICITY PULSE TECHNIQUE |
title | CLOCK-GATING CELL WITH LOW AREA, LOW POWER, AND LOW SETUP TIME |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-12T12%3A45%3A43IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=DILLEN,%20Steven%20James&rft.date=2020-08-05&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EEP3245735B1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |