SUBSTRATE STRUCTURES AND METHODS OF MANUFACTURE
The invention relates to a method of forming an insulated metal substrate (IMS) for a power electronic, comprising: partially etching a first surface of a copper layer to form a pattern comprising a first thickness and a second thickness greater than the first thickness, the first thickness and the...
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| creator | LIN, Yusheng TAKAKUSAKI, Sadamichi |
| description | The invention relates to a method of forming an insulated metal substrate (IMS) for a power electronic, comprising: partially etching a first surface of a copper layer to form a pattern comprising a first thickness and a second thickness greater than the first thickness, the first thickness and the second thickness both measured perpendicular to a second surface of the copper layer opposite the first surface of the copper layer; laminating the first surface of the copper layer with a second surface of a dielectric layer, the dielectric layer coupled to a metallic baseplate at a first surface of the dielectric layer opposite the second surface of the dielectric layer and at a second surface of the metallic baseplate; and forming traces in the copper layer by etching through the copper layer at the first thickness and etching through the copper layer at the second thickness, wherein the traces comprise two different trace thicknesses, where the trace thicknesses are measured perpendicularly to the first surface of the dielectric layer. |
| format | Patent |
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laminating the first surface of the copper layer with a second surface of a dielectric layer, the dielectric layer coupled to a metallic baseplate at a first surface of the dielectric layer opposite the second surface of the dielectric layer and at a second surface of the metallic baseplate; and forming traces in the copper layer by etching through the copper layer at the first thickness and etching through the copper layer at the second thickness, wherein the traces comprise two different trace thicknesses, where the trace thicknesses are measured perpendicularly to the first surface of the dielectric layer.</description><language>eng ; fre ; ger</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2017</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170802&DB=EPODOC&CC=EP&NR=3198640A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76516</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170802&DB=EPODOC&CC=EP&NR=3198640A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>LIN, Yusheng</creatorcontrib><creatorcontrib>TAKAKUSAKI, Sadamichi</creatorcontrib><title>SUBSTRATE STRUCTURES AND METHODS OF MANUFACTURE</title><description>The invention relates to a method of forming an insulated metal substrate (IMS) for a power electronic, comprising: partially etching a first surface of a copper layer to form a pattern comprising a first thickness and a second thickness greater than the first thickness, the first thickness and the second thickness both measured perpendicular to a second surface of the copper layer opposite the first surface of the copper layer; laminating the first surface of the copper layer with a second surface of a dielectric layer, the dielectric layer coupled to a metallic baseplate at a first surface of the dielectric layer opposite the second surface of the dielectric layer and at a second surface of the metallic baseplate; and forming traces in the copper layer by etching through the copper layer at the first thickness and etching through the copper layer at the second thickness, wherein the traces comprise two different trace thicknesses, where the trace thicknesses are measured perpendicularly to the first surface of the dielectric layer.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2017</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNAPDnUKDglyDHFVAFKhziGhQa7BCo5-Lgq-riEe_i7BCv5uCr6OfqFujmA5HgbWtMSc4lReKM3NoODmGuLsoZtakB-fWlyQmJyal1oS7xpgbGhpYWZi4GhoTIQSAOcIJfQ</recordid><startdate>20170802</startdate><enddate>20170802</enddate><creator>LIN, Yusheng</creator><creator>TAKAKUSAKI, Sadamichi</creator><scope>EVB</scope></search><sort><creationdate>20170802</creationdate><title>SUBSTRATE STRUCTURES AND METHODS OF MANUFACTURE</title><author>LIN, Yusheng ; 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laminating the first surface of the copper layer with a second surface of a dielectric layer, the dielectric layer coupled to a metallic baseplate at a first surface of the dielectric layer opposite the second surface of the dielectric layer and at a second surface of the metallic baseplate; and forming traces in the copper layer by etching through the copper layer at the first thickness and etching through the copper layer at the second thickness, wherein the traces comprise two different trace thicknesses, where the trace thicknesses are measured perpendicularly to the first surface of the dielectric layer.</abstract><oa>free_for_read</oa></addata></record> |
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| language | eng ; fre ; ger |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | SUBSTRATE STRUCTURES AND METHODS OF MANUFACTURE |
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