ULTRA WIDEBAND TRUE TIME DELAY LINES
A time delay circuit comprising: a first semiconductor substrate (42) including a top planar surface and a bottom surface; a first delay line (46) formed on the top planar surface of the first substrate and having a first end and a second end; a metal layer formed on the bottom surface of the first...
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| creator | Lan, Xing Kintis, Mark Hansen, Chad |
| description | A time delay circuit comprising:
a first semiconductor substrate (42) including a top planar surface and a bottom surface;
a first delay line (46) formed on the top planar surface of the first substrate and
having a first end and a second end;
a metal layer formed on the bottom surface of the first substrate and including an opening;
a second semiconductor substrate (44) including a top planar surface and being spaced apart from the first substrate so as to provide an air gap therebetween;
a second delay line (58) formed on the top planar surface of the second substrate and having a first end and a second end; and
an inter-cavity interconnection electrically coupled to the second ends of the first and
second delay lines and extending through the first substrate, the opening in the metal layer and the air gap between the first and second substrates. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_EP3168926A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>EP3168926A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_EP3168926A13</originalsourceid><addsrcrecordid>eNrjZFAJ9QkJclQI93RxdXL0c1EICQp1VQjx9HVVcHH1cYxU8PH0cw3mYWBNS8wpTuWF0twMCm6uIc4euqkF-fGpxQWJyal5qSXxrgHGhmYWlkZmjobGRCgBACktIng</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>ULTRA WIDEBAND TRUE TIME DELAY LINES</title><source>esp@cenet</source><creator>Lan, Xing ; Kintis, Mark ; Hansen, Chad</creator><creatorcontrib>Lan, Xing ; Kintis, Mark ; Hansen, Chad</creatorcontrib><description>A time delay circuit comprising:
a first semiconductor substrate (42) including a top planar surface and a bottom surface;
a first delay line (46) formed on the top planar surface of the first substrate and
having a first end and a second end;
a metal layer formed on the bottom surface of the first substrate and including an opening;
a second semiconductor substrate (44) including a top planar surface and being spaced apart from the first substrate so as to provide an air gap therebetween;
a second delay line (58) formed on the top planar surface of the second substrate and having a first end and a second end; and
an inter-cavity interconnection electrically coupled to the second ends of the first and
second delay lines and extending through the first substrate, the opening in the metal layer and the air gap between the first and second substrates.</description><language>eng ; fre ; ger</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRICITY ; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE ; WAVEGUIDES</subject><creationdate>2017</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170517&DB=EPODOC&CC=EP&NR=3168926A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20170517&DB=EPODOC&CC=EP&NR=3168926A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Lan, Xing</creatorcontrib><creatorcontrib>Kintis, Mark</creatorcontrib><creatorcontrib>Hansen, Chad</creatorcontrib><title>ULTRA WIDEBAND TRUE TIME DELAY LINES</title><description>A time delay circuit comprising:
a first semiconductor substrate (42) including a top planar surface and a bottom surface;
a first delay line (46) formed on the top planar surface of the first substrate and
having a first end and a second end;
a metal layer formed on the bottom surface of the first substrate and including an opening;
a second semiconductor substrate (44) including a top planar surface and being spaced apart from the first substrate so as to provide an air gap therebetween;
a second delay line (58) formed on the top planar surface of the second substrate and having a first end and a second end; and
an inter-cavity interconnection electrically coupled to the second ends of the first and
second delay lines and extending through the first substrate, the opening in the metal layer and the air gap between the first and second substrates.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRICITY</subject><subject>RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE</subject><subject>WAVEGUIDES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2017</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFAJ9QkJclQI93RxdXL0c1EICQp1VQjx9HVVcHH1cYxU8PH0cw3mYWBNS8wpTuWF0twMCm6uIc4euqkF-fGpxQWJyal5qSXxrgHGhmYWlkZmjobGRCgBACktIng</recordid><startdate>20170517</startdate><enddate>20170517</enddate><creator>Lan, Xing</creator><creator>Kintis, Mark</creator><creator>Hansen, Chad</creator><scope>EVB</scope></search><sort><creationdate>20170517</creationdate><title>ULTRA WIDEBAND TRUE TIME DELAY LINES</title><author>Lan, Xing ; Kintis, Mark ; Hansen, Chad</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP3168926A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre ; ger</language><creationdate>2017</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRICITY</topic><topic>RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE</topic><topic>WAVEGUIDES</topic><toplevel>online_resources</toplevel><creatorcontrib>Lan, Xing</creatorcontrib><creatorcontrib>Kintis, Mark</creatorcontrib><creatorcontrib>Hansen, Chad</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Lan, Xing</au><au>Kintis, Mark</au><au>Hansen, Chad</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>ULTRA WIDEBAND TRUE TIME DELAY LINES</title><date>2017-05-17</date><risdate>2017</risdate><abstract>A time delay circuit comprising:
a first semiconductor substrate (42) including a top planar surface and a bottom surface;
a first delay line (46) formed on the top planar surface of the first substrate and
having a first end and a second end;
a metal layer formed on the bottom surface of the first substrate and including an opening;
a second semiconductor substrate (44) including a top planar surface and being spaced apart from the first substrate so as to provide an air gap therebetween;
a second delay line (58) formed on the top planar surface of the second substrate and having a first end and a second end; and
an inter-cavity interconnection electrically coupled to the second ends of the first and
second delay lines and extending through the first substrate, the opening in the metal layer and the air gap between the first and second substrates.</abstract><oa>free_for_read</oa></addata></record> |
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| language | eng ; fre ; ger |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRICITY RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE WAVEGUIDES |
| title | ULTRA WIDEBAND TRUE TIME DELAY LINES |
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