INSULATING LAYER FOR PRINTED WIRE BOARD, AND PRINTED WIRE BOARD
The present invention provides an insulating layer for printed circuit boards having a difference of within 20% between the flexural modulus at 25°C and the flexural modulus under heat at 250°C.
Gespeichert in:
| Hauptverfasser: | , , , |
|---|---|
| Format: | Patent |
| Sprache: | eng ; fre ; ger |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | TOMIZAWA, Katsuya ITO, Meguru SHIGA, Eisuke CHIBA, Tomo |
| description | The present invention provides an insulating layer for printed circuit boards having a difference of within 20% between the flexural modulus at 25°C and the flexural modulus under heat at 250°C. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_EP3094162B1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>EP3094162B1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_EP3094162B13</originalsourceid><addsrcrecordid>eNrjZLD39AsO9XEM8fRzV_BxjHQNUnDzD1IICPL0C3F1UQj3DHJVcPJ3DHLRUXD0c8EizsPAmpaYU5zKC6W5GRTcXEOcPXRTC_LjU4sLEpNT81JL4l0DjA0sTQzNjJwMjYlQAgAVkymt</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>INSULATING LAYER FOR PRINTED WIRE BOARD, AND PRINTED WIRE BOARD</title><source>esp@cenet</source><creator>TOMIZAWA, Katsuya ; ITO, Meguru ; SHIGA, Eisuke ; CHIBA, Tomo</creator><creatorcontrib>TOMIZAWA, Katsuya ; ITO, Meguru ; SHIGA, Eisuke ; CHIBA, Tomo</creatorcontrib><description>The present invention provides an insulating layer for printed circuit boards having a difference of within 20% between the flexural modulus at 25°C and the flexural modulus under heat at 250°C.</description><language>eng ; fre ; ger</language><subject>AFTER-TREATMENT NOT COVERED BY SUBCLASSES C08B, C08C, C08F,C08G ; BASIC ELECTRIC ELEMENTS ; CABLES ; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ; CHEMISTRY ; COMPOSITIONS BASED THEREON ; CONDUCTORS ; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; GENERAL PROCESSES OF COMPOUNDING ; INSULATORS ; LAYERED PRODUCTS ; LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT ORNON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM ; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ; METALLURGY ; ORGANIC MACROMOLECULAR COMPOUNDS ; PERFORMING OPERATIONS ; PRINTED CIRCUITS ; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING ORDIELECTRIC PROPERTIES ; THEIR PREPARATION OR CHEMICAL WORKING-UP ; TRANSPORTING ; WORKING-UP</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230809&DB=EPODOC&CC=EP&NR=3094162B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230809&DB=EPODOC&CC=EP&NR=3094162B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>TOMIZAWA, Katsuya</creatorcontrib><creatorcontrib>ITO, Meguru</creatorcontrib><creatorcontrib>SHIGA, Eisuke</creatorcontrib><creatorcontrib>CHIBA, Tomo</creatorcontrib><title>INSULATING LAYER FOR PRINTED WIRE BOARD, AND PRINTED WIRE BOARD</title><description>The present invention provides an insulating layer for printed circuit boards having a difference of within 20% between the flexural modulus at 25°C and the flexural modulus under heat at 250°C.</description><subject>AFTER-TREATMENT NOT COVERED BY SUBCLASSES C08B, C08C, C08F,C08G</subject><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CABLES</subject><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</subject><subject>CHEMISTRY</subject><subject>COMPOSITIONS BASED THEREON</subject><subject>CONDUCTORS</subject><subject>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>GENERAL PROCESSES OF COMPOUNDING</subject><subject>INSULATORS</subject><subject>LAYERED PRODUCTS</subject><subject>LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT ORNON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM</subject><subject>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</subject><subject>METALLURGY</subject><subject>ORGANIC MACROMOLECULAR COMPOUNDS</subject><subject>PERFORMING OPERATIONS</subject><subject>PRINTED CIRCUITS</subject><subject>SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING ORDIELECTRIC PROPERTIES</subject><subject>THEIR PREPARATION OR CHEMICAL WORKING-UP</subject><subject>TRANSPORTING</subject><subject>WORKING-UP</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLD39AsO9XEM8fRzV_BxjHQNUnDzD1IICPL0C3F1UQj3DHJVcPJ3DHLRUXD0c8EizsPAmpaYU5zKC6W5GRTcXEOcPXRTC_LjU4sLEpNT81JL4l0DjA0sTQzNjJwMjYlQAgAVkymt</recordid><startdate>20230809</startdate><enddate>20230809</enddate><creator>TOMIZAWA, Katsuya</creator><creator>ITO, Meguru</creator><creator>SHIGA, Eisuke</creator><creator>CHIBA, Tomo</creator><scope>EVB</scope></search><sort><creationdate>20230809</creationdate><title>INSULATING LAYER FOR PRINTED WIRE BOARD, AND PRINTED WIRE BOARD</title><author>TOMIZAWA, Katsuya ; ITO, Meguru ; SHIGA, Eisuke ; CHIBA, Tomo</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP3094162B13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre ; ger</language><creationdate>2023</creationdate><topic>AFTER-TREATMENT NOT COVERED BY SUBCLASSES C08B, C08C, C08F,C08G</topic><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CABLES</topic><topic>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</topic><topic>CHEMISTRY</topic><topic>COMPOSITIONS BASED THEREON</topic><topic>CONDUCTORS</topic><topic>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>GENERAL PROCESSES OF COMPOUNDING</topic><topic>INSULATORS</topic><topic>LAYERED PRODUCTS</topic><topic>LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT ORNON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM</topic><topic>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</topic><topic>METALLURGY</topic><topic>ORGANIC MACROMOLECULAR COMPOUNDS</topic><topic>PERFORMING OPERATIONS</topic><topic>PRINTED CIRCUITS</topic><topic>SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING ORDIELECTRIC PROPERTIES</topic><topic>THEIR PREPARATION OR CHEMICAL WORKING-UP</topic><topic>TRANSPORTING</topic><topic>WORKING-UP</topic><toplevel>online_resources</toplevel><creatorcontrib>TOMIZAWA, Katsuya</creatorcontrib><creatorcontrib>ITO, Meguru</creatorcontrib><creatorcontrib>SHIGA, Eisuke</creatorcontrib><creatorcontrib>CHIBA, Tomo</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>TOMIZAWA, Katsuya</au><au>ITO, Meguru</au><au>SHIGA, Eisuke</au><au>CHIBA, Tomo</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>INSULATING LAYER FOR PRINTED WIRE BOARD, AND PRINTED WIRE BOARD</title><date>2023-08-09</date><risdate>2023</risdate><abstract>The present invention provides an insulating layer for printed circuit boards having a difference of within 20% between the flexural modulus at 25°C and the flexural modulus under heat at 250°C.</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng ; fre ; ger |
| recordid | cdi_epo_espacenet_EP3094162B1 |
| source | esp@cenet |
| subjects | AFTER-TREATMENT NOT COVERED BY SUBCLASSES C08B, C08C, C08F,C08G BASIC ELECTRIC ELEMENTS CABLES CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS CHEMISTRY COMPOSITIONS BASED THEREON CONDUCTORS ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ELECTRICITY GENERAL PROCESSES OF COMPOUNDING INSULATORS LAYERED PRODUCTS LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT ORNON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS METALLURGY ORGANIC MACROMOLECULAR COMPOUNDS PERFORMING OPERATIONS PRINTED CIRCUITS SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING ORDIELECTRIC PROPERTIES THEIR PREPARATION OR CHEMICAL WORKING-UP TRANSPORTING WORKING-UP |
| title | INSULATING LAYER FOR PRINTED WIRE BOARD, AND PRINTED WIRE BOARD |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-20T11%3A27%3A10IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=TOMIZAWA,%20Katsuya&rft.date=2023-08-09&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EEP3094162B1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |