LATCH COMPARATOR CIRCUITS AND METHODS

LATCH COMPARATOR CIRCUITS AND METHODS

The present disclosure includes circuits and methods for latching signals. In one embodiment, two inverters are configured back to back to latch a signal. Each inverter includes a capacitor configured between control terminals of inverter transistors. In one embodiment, the circuit is part of a comp...

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Hauptverfasser: RAJAEE, OMID, ALLADI, DINESH J
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
PULSE TECHNIQUE
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creator RAJAEE, OMID
ALLADI, DINESH J
description The present disclosure includes circuits and methods for latching signals. In one embodiment, two inverters are configured back to back to latch a signal. Each inverter includes a capacitor configured between control terminals of inverter transistors. In one embodiment, the circuit is part of a comparator. First and second voltages are received on control terminals of differential transistors, and a differential output signal is coupled to two back to back inverters. In one embodiment, a circuit is disabled and a voltage on a control terminal of a transistor in an inverter is set below a reference, such as a power supply, to increase the speed of the circuit.
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Each inverter includes a capacitor configured between control terminals of inverter transistors. In one embodiment, the circuit is part of a comparator. First and second voltages are received on control terminals of differential transistors, and a differential output signal is coupled to two back to back inverters. In one embodiment, a circuit is disabled and a voltage on a control terminal of a transistor in an inverter is set below a reference, such as a power supply, to increase the speed of the circuit.</description><language>eng ; fre ; ger</language><subject>BASIC ELECTRONIC CIRCUITRY ; ELECTRICITY ; PULSE TECHNIQUE</subject><creationdate>2016</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20160907&amp;DB=EPODOC&amp;CC=EP&amp;NR=3063870A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,309,781,886,25569,76552</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20160907&amp;DB=EPODOC&amp;CC=EP&amp;NR=3063870A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>RAJAEE, OMID</creatorcontrib><creatorcontrib>ALLADI, DINESH J</creatorcontrib><title>LATCH COMPARATOR CIRCUITS AND METHODS</title><description>The present disclosure includes circuits and methods for latching signals. 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In one embodiment, two inverters are configured back to back to latch a signal. Each inverter includes a capacitor configured between control terminals of inverter transistors. In one embodiment, the circuit is part of a comparator. First and second voltages are received on control terminals of differential transistors, and a differential output signal is coupled to two back to back inverters. In one embodiment, a circuit is disabled and a voltage on a control terminal of a transistor in an inverter is set below a reference, such as a power supply, to increase the speed of the circuit.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
PULSE TECHNIQUE
title LATCH COMPARATOR CIRCUITS AND METHODS
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