IMPROVED REFRESH RATE PERFORMANCE BASED ON IN-SYSTEM WEAK BIT DETECTION

IMPROVED REFRESH RATE PERFORMANCE BASED ON IN-SYSTEM WEAK BIT DETECTION

A memory subsystem can test a memory device in situ, testing the performance of the device in the system it is built into during production. Thus, the refresh rate can be adjusted specific to the memory device(s) of a specific system, rather than defaulting to a refresh frequency specified by a stan...

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Hauptverfasser: MOZAK, CHRISTOPHER P, SCHOENBORN, THEODORE Z
Format: Patent
Sprache:eng ; fre ; ger
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INFORMATION STORAGE
PHYSICS
STATIC STORES
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creator MOZAK, CHRISTOPHER P
SCHOENBORN, THEODORE Z
description A memory subsystem can test a memory device in situ, testing the performance of the device in the system it is built into during production. Thus, the refresh rate can be adjusted specific to the memory device(s) of a specific system, rather than defaulting to a refresh frequency specified by a standard for the memory device(s). A test component embedded within the host memory subsystem can perform a test and identify specific bits or lines of memory that produce errors when a lower frequency refresh rate is used. The system maps out the identified bits or lines to prevent the bits/lines from being used in runtime of the system. The memory subsystem can then set its refresh rate to an adjusted refresh rate at which a threshold number of errors can be removed by mapping out the bits/lines.
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subjects INFORMATION STORAGE
PHYSICS
STATIC STORES
title IMPROVED REFRESH RATE PERFORMANCE BASED ON IN-SYSTEM WEAK BIT DETECTION
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