DISTRIBUTED CACHE COHERENCY DIRECTORY WITH FAILURE REDUNDANCY
A system includes a number of processors with each processor including a cache memory. The system also includes a number of directory controllers coupled to the processors. Each directory controller may be configured to administer a corresponding cache coherency directory. Each cache coherency direc...
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creator | PHILLIPS, Stephen, E LOEWENSTEIN, Paul, N WICKI, Thomas, M ANESHANSLEY, Nicholas, E SIVARAMAKRISHNAN, Ramaswamy |
description | A system includes a number of processors with each processor including a cache memory. The system also includes a number of directory controllers coupled to the processors. Each directory controller may be configured to administer a corresponding cache coherency directory. Each cache coherency directory may be configured to track a corresponding set of memory addresses. Each processor may be configured with information indicating the corresponding set of memory addresses tracked by each cache coherency directory. Directory redundancy operations in such a system may include identifying a failure of one of the cache coherency directories; reassigning the memory address set previously tracked by the failed cache coherency directory among the non-failed cache coherency directories; and reconfiguring each processor with information describing the reassignment of the memory address set among the non-failed cache coherency directories. |
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Directory redundancy operations in such a system may include identifying a failure of one of the cache coherency directories; reassigning the memory address set previously tracked by the failed cache coherency directory among the non-failed cache coherency directories; and reconfiguring each processor with information describing the reassignment of the memory address set among the non-failed cache coherency directories.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2018</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLB18QwOCfJ0Cg1xdVFwdnT2cFVw9vdwDXL1c45UcPEMcnUO8Q-KVAj3DPFQcHP09AkNclUIcnUJ9XNxBKrgYWBNS8wpTuWF0twMCm6uIc4euqkF-fGpxQWJyal5qSXxrgFGlsZmxkYGTobGRCgBAPItKZ0</recordid><startdate>20181121</startdate><enddate>20181121</enddate><creator>PHILLIPS, Stephen, E</creator><creator>LOEWENSTEIN, Paul, N</creator><creator>WICKI, Thomas, M</creator><creator>ANESHANSLEY, Nicholas, E</creator><creator>SIVARAMAKRISHNAN, Ramaswamy</creator><scope>EVB</scope></search><sort><creationdate>20181121</creationdate><title>DISTRIBUTED CACHE COHERENCY DIRECTORY WITH FAILURE REDUNDANCY</title><author>PHILLIPS, Stephen, E ; LOEWENSTEIN, Paul, N ; WICKI, Thomas, M ; ANESHANSLEY, Nicholas, E ; SIVARAMAKRISHNAN, Ramaswamy</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP2936320B13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre ; ger</language><creationdate>2018</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>PHILLIPS, Stephen, E</creatorcontrib><creatorcontrib>LOEWENSTEIN, Paul, N</creatorcontrib><creatorcontrib>WICKI, Thomas, M</creatorcontrib><creatorcontrib>ANESHANSLEY, Nicholas, E</creatorcontrib><creatorcontrib>SIVARAMAKRISHNAN, Ramaswamy</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>PHILLIPS, Stephen, E</au><au>LOEWENSTEIN, Paul, N</au><au>WICKI, Thomas, M</au><au>ANESHANSLEY, Nicholas, E</au><au>SIVARAMAKRISHNAN, Ramaswamy</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>DISTRIBUTED CACHE COHERENCY DIRECTORY WITH FAILURE REDUNDANCY</title><date>2018-11-21</date><risdate>2018</risdate><abstract>A system includes a number of processors with each processor including a cache memory. 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subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
title | DISTRIBUTED CACHE COHERENCY DIRECTORY WITH FAILURE REDUNDANCY |
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