TECHNIQUES ASSOCIATED WITH A READ AND WRITE WINDOW BUDGET FOR A TWO LEVEL MEMORY SYSTEM
Techniques associated with a read and write window budget for a two level memory (2LM) system may include establishing a read and write window budget for the 2LM system that includes a first level memory and a second level memory. The established read and write window budget may include a combinatio...
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Patent |
| Sprache: | eng ; fre ; ger |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | PANGAL, KIRAN DAMLE, PRASHANT |
| description | Techniques associated with a read and write window budget for a two level memory (2LM) system may include establishing a read and write window budget for the 2LM system that includes a first level memory and a second level memory. The established read and write window budget may include a combination of a first set of memory addresses and a second set of memory addresses of the second level of memory. The first set of memory addresses may be associated with non-volatile memory cells having wider cell threshold voltage distributions compared to cell threshold voltage distributions for non-volatile memory cells associated with the second set of memory addresses. According to some examples, the established read and write window budget may be part of a strategy to meet both a completion time threshold for a given amount of memory and an acceptable error rate threshold for the given amount of memory when fulfilling read or write requests to the second level memory. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_EP2901286A4</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>EP2901286A4</sourcerecordid><originalsourceid>FETCH-epo_espacenet_EP2901286A43</originalsourceid><addsrcrecordid>eNqNikEKwjAQAHPxIOof9gOCVhF7XJOtDTSJJltDT6VIPIkW6v8xBx_gaZhh5iIyydrqa0sBMAQnNTIpiJprQPCECtBm95opV6tchFOrzsRQOZ8Xjg4aulEDhozzHYQuMJmlmD2G55RWPy4EVMSyXqfx3adpHO7plT49XYpysy2OB9zv_li-QocwXw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>TECHNIQUES ASSOCIATED WITH A READ AND WRITE WINDOW BUDGET FOR A TWO LEVEL MEMORY SYSTEM</title><source>esp@cenet</source><creator>PANGAL, KIRAN ; DAMLE, PRASHANT</creator><creatorcontrib>PANGAL, KIRAN ; DAMLE, PRASHANT</creatorcontrib><description>Techniques associated with a read and write window budget for a two level memory (2LM) system may include establishing a read and write window budget for the 2LM system that includes a first level memory and a second level memory. The established read and write window budget may include a combination of a first set of memory addresses and a second set of memory addresses of the second level of memory. The first set of memory addresses may be associated with non-volatile memory cells having wider cell threshold voltage distributions compared to cell threshold voltage distributions for non-volatile memory cells associated with the second set of memory addresses. According to some examples, the established read and write window budget may be part of a strategy to meet both a completion time threshold for a given amount of memory and an acceptable error rate threshold for the given amount of memory when fulfilling read or write requests to the second level memory.</description><language>eng ; fre ; ger</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2016</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20160420&DB=EPODOC&CC=EP&NR=2901286A4$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76318</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20160420&DB=EPODOC&CC=EP&NR=2901286A4$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>PANGAL, KIRAN</creatorcontrib><creatorcontrib>DAMLE, PRASHANT</creatorcontrib><title>TECHNIQUES ASSOCIATED WITH A READ AND WRITE WINDOW BUDGET FOR A TWO LEVEL MEMORY SYSTEM</title><description>Techniques associated with a read and write window budget for a two level memory (2LM) system may include establishing a read and write window budget for the 2LM system that includes a first level memory and a second level memory. The established read and write window budget may include a combination of a first set of memory addresses and a second set of memory addresses of the second level of memory. The first set of memory addresses may be associated with non-volatile memory cells having wider cell threshold voltage distributions compared to cell threshold voltage distributions for non-volatile memory cells associated with the second set of memory addresses. According to some examples, the established read and write window budget may be part of a strategy to meet both a completion time threshold for a given amount of memory and an acceptable error rate threshold for the given amount of memory when fulfilling read or write requests to the second level memory.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2016</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNikEKwjAQAHPxIOof9gOCVhF7XJOtDTSJJltDT6VIPIkW6v8xBx_gaZhh5iIyydrqa0sBMAQnNTIpiJprQPCECtBm95opV6tchFOrzsRQOZ8Xjg4aulEDhozzHYQuMJmlmD2G55RWPy4EVMSyXqfx3adpHO7plT49XYpysy2OB9zv_li-QocwXw</recordid><startdate>20160420</startdate><enddate>20160420</enddate><creator>PANGAL, KIRAN</creator><creator>DAMLE, PRASHANT</creator><scope>EVB</scope></search><sort><creationdate>20160420</creationdate><title>TECHNIQUES ASSOCIATED WITH A READ AND WRITE WINDOW BUDGET FOR A TWO LEVEL MEMORY SYSTEM</title><author>PANGAL, KIRAN ; DAMLE, PRASHANT</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP2901286A43</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre ; ger</language><creationdate>2016</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>PANGAL, KIRAN</creatorcontrib><creatorcontrib>DAMLE, PRASHANT</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>PANGAL, KIRAN</au><au>DAMLE, PRASHANT</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>TECHNIQUES ASSOCIATED WITH A READ AND WRITE WINDOW BUDGET FOR A TWO LEVEL MEMORY SYSTEM</title><date>2016-04-20</date><risdate>2016</risdate><abstract>Techniques associated with a read and write window budget for a two level memory (2LM) system may include establishing a read and write window budget for the 2LM system that includes a first level memory and a second level memory. The established read and write window budget may include a combination of a first set of memory addresses and a second set of memory addresses of the second level of memory. The first set of memory addresses may be associated with non-volatile memory cells having wider cell threshold voltage distributions compared to cell threshold voltage distributions for non-volatile memory cells associated with the second set of memory addresses. According to some examples, the established read and write window budget may be part of a strategy to meet both a completion time threshold for a given amount of memory and an acceptable error rate threshold for the given amount of memory when fulfilling read or write requests to the second level memory.</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng ; fre ; ger |
| recordid | cdi_epo_espacenet_EP2901286A4 |
| source | esp@cenet |
| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | TECHNIQUES ASSOCIATED WITH A READ AND WRITE WINDOW BUDGET FOR A TWO LEVEL MEMORY SYSTEM |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-10T21%3A18%3A31IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=PANGAL,%20KIRAN&rft.date=2016-04-20&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EEP2901286A4%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |