SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

A technique for improving characteristics of a semiconductor device (DMOSFET) is provided. A semiconductor device is configured so as to include: an n-type source layer (102) disposed on an upper portion of a first surface side of an SiC substrate (106) ; a p body layer (103) which surrounds the sou...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: MATSUMOTO, DAISUKE, TEGA, NAOKI, SHIMAMOTO, YASUHIRO
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator MATSUMOTO, DAISUKE
TEGA, NAOKI
SHIMAMOTO, YASUHIRO
description A technique for improving characteristics of a semiconductor device (DMOSFET) is provided. A semiconductor device is configured so as to include: an n-type source layer (102) disposed on an upper portion of a first surface side of an SiC substrate (106) ; a p body layer (103) which surrounds the source layer and has a channel region; an n - -type drift layer (107) which is in contact with the p body layer (103); a gate electrode (116) which is disposed on an upper portion of the channel region via a gate insulating film; and a first p + layer (109) which is disposed in the p body layer (103), extends to a portion below the n + source layer (102), and serves as a buried semiconductor region having an impurity concentration higher than that of the p body layer (103). In this manner, since the first p + layer (109) is formed in the middle of the p body layer (103), it is possible to reduce the diffusion resistance of the p body layer (103). Thus, it is possible to make a parasitic bipolar transistor harder to turn on.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_EP2747146A4</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>EP2747146A4</sourcerecordid><originalsourceid>FETCH-epo_espacenet_EP2747146A43</originalsourceid><addsrcrecordid>eNrjZHALdvX1dPb3cwl1DvEPUnBxDfN0dlVw9HNR8HUN8fB3UXADivo6-oW6OTqHhAZ5-rkrYNPBw8CalphTnMoLpbkZFNxcQ5w9dFML8uNTiwsSk1PzUkviXQOMzE3MDU3MHE2MiVACAHAiLCY</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE</title><source>esp@cenet</source><creator>MATSUMOTO, DAISUKE ; TEGA, NAOKI ; SHIMAMOTO, YASUHIRO</creator><creatorcontrib>MATSUMOTO, DAISUKE ; TEGA, NAOKI ; SHIMAMOTO, YASUHIRO</creatorcontrib><description>A technique for improving characteristics of a semiconductor device (DMOSFET) is provided. A semiconductor device is configured so as to include: an n-type source layer (102) disposed on an upper portion of a first surface side of an SiC substrate (106) ; a p body layer (103) which surrounds the source layer and has a channel region; an n - -type drift layer (107) which is in contact with the p body layer (103); a gate electrode (116) which is disposed on an upper portion of the channel region via a gate insulating film; and a first p + layer (109) which is disposed in the p body layer (103), extends to a portion below the n + source layer (102), and serves as a buried semiconductor region having an impurity concentration higher than that of the p body layer (103). In this manner, since the first p + layer (109) is formed in the middle of the p body layer (103), it is possible to reduce the diffusion resistance of the p body layer (103). Thus, it is possible to make a parasitic bipolar transistor harder to turn on.</description><language>eng ; fre ; ger</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2015</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20151125&amp;DB=EPODOC&amp;CC=EP&amp;NR=2747146A4$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20151125&amp;DB=EPODOC&amp;CC=EP&amp;NR=2747146A4$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MATSUMOTO, DAISUKE</creatorcontrib><creatorcontrib>TEGA, NAOKI</creatorcontrib><creatorcontrib>SHIMAMOTO, YASUHIRO</creatorcontrib><title>SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE</title><description>A technique for improving characteristics of a semiconductor device (DMOSFET) is provided. A semiconductor device is configured so as to include: an n-type source layer (102) disposed on an upper portion of a first surface side of an SiC substrate (106) ; a p body layer (103) which surrounds the source layer and has a channel region; an n - -type drift layer (107) which is in contact with the p body layer (103); a gate electrode (116) which is disposed on an upper portion of the channel region via a gate insulating film; and a first p + layer (109) which is disposed in the p body layer (103), extends to a portion below the n + source layer (102), and serves as a buried semiconductor region having an impurity concentration higher than that of the p body layer (103). In this manner, since the first p + layer (109) is formed in the middle of the p body layer (103), it is possible to reduce the diffusion resistance of the p body layer (103). Thus, it is possible to make a parasitic bipolar transistor harder to turn on.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2015</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHALdvX1dPb3cwl1DvEPUnBxDfN0dlVw9HNR8HUN8fB3UXADivo6-oW6OTqHhAZ5-rkrYNPBw8CalphTnMoLpbkZFNxcQ5w9dFML8uNTiwsSk1PzUkviXQOMzE3MDU3MHE2MiVACAHAiLCY</recordid><startdate>20151125</startdate><enddate>20151125</enddate><creator>MATSUMOTO, DAISUKE</creator><creator>TEGA, NAOKI</creator><creator>SHIMAMOTO, YASUHIRO</creator><scope>EVB</scope></search><sort><creationdate>20151125</creationdate><title>SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE</title><author>MATSUMOTO, DAISUKE ; TEGA, NAOKI ; SHIMAMOTO, YASUHIRO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP2747146A43</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre ; ger</language><creationdate>2015</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>MATSUMOTO, DAISUKE</creatorcontrib><creatorcontrib>TEGA, NAOKI</creatorcontrib><creatorcontrib>SHIMAMOTO, YASUHIRO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>MATSUMOTO, DAISUKE</au><au>TEGA, NAOKI</au><au>SHIMAMOTO, YASUHIRO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE</title><date>2015-11-25</date><risdate>2015</risdate><abstract>A technique for improving characteristics of a semiconductor device (DMOSFET) is provided. A semiconductor device is configured so as to include: an n-type source layer (102) disposed on an upper portion of a first surface side of an SiC substrate (106) ; a p body layer (103) which surrounds the source layer and has a channel region; an n - -type drift layer (107) which is in contact with the p body layer (103); a gate electrode (116) which is disposed on an upper portion of the channel region via a gate insulating film; and a first p + layer (109) which is disposed in the p body layer (103), extends to a portion below the n + source layer (102), and serves as a buried semiconductor region having an impurity concentration higher than that of the p body layer (103). In this manner, since the first p + layer (109) is formed in the middle of the p body layer (103), it is possible to reduce the diffusion resistance of the p body layer (103). Thus, it is possible to make a parasitic bipolar transistor harder to turn on.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng ; fre ; ger
recordid cdi_epo_espacenet_EP2747146A4
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-09T06%3A04%3A55IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=MATSUMOTO,%20DAISUKE&rft.date=2015-11-25&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EEP2747146A4%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true