MODIFIED DYNAMIC ELEMENT MATCHING FOR REDUCED LATENCY IN A PIPELINE ANALOG TO DIGITAL CONVERTER

MODIFIED DYNAMIC ELEMENT MATCHING FOR REDUCED LATENCY IN A PIPELINE ANALOG TO DIGITAL CONVERTER

A circuit in an analog-to-digital converter (ADC) includes an amplifier configured to receive an output of a backend DAC; a harmonic distortion correction circuit (HDC) coupled to the amplifier and configured to correct distortion components due to the residue amplifier present in a digital signal f...

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Hauptverfasser: PANIGADA, Andrea, GRILO, Jorge, MEACHAM, Daniel
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
BASIC ELECTRONIC CIRCUITRY
CODE CONVERSION IN GENERAL
CODING
DECODING
ELECTRICITY
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creator PANIGADA, Andrea
GRILO, Jorge
MEACHAM, Daniel
description A circuit in an analog-to-digital converter (ADC) includes an amplifier configured to receive an output of a backend DAC; a harmonic distortion correction circuit (HDC) coupled to the amplifier and configured to correct distortion components due to the residue amplifier present in a digital signal from the backend ADC, the HDC circuit providing an output to an adder, the adder receiving a coarse digital output from a coarse ADC; and a DAC noise cancellation circuit (DNC) configured to provide an output to the adder, wherein the DNC circuit is configured to correct distortion components due to the DAC present in the digital signal from the backend ADC; wherein the output of the adder is an ADC digital output and wherein the ADC digital output forms an input to the HDC and the DNC.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_EP2719081B1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>EP2719081B1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_EP2719081B13</originalsourceid><addsrcrecordid>eNqNzDEKwkAQRuE0FqLe4b-AYLRQy3F3Egd2Z8OyEVKFIGslGoj3xxQewOo1H29Z9D5YqYQtbKfkxYAde9YET8lcRWtUISKybc2MHCVW00EUhEYadqIMUnKhRgqwUksiBxP0xjFxXBeLx_Cc8ubXVYGK5_E2j-8-T-Nwz6_86bnZH8vz7lReysMf5AupdDJP</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>MODIFIED DYNAMIC ELEMENT MATCHING FOR REDUCED LATENCY IN A PIPELINE ANALOG TO DIGITAL CONVERTER</title><source>esp@cenet</source><creator>PANIGADA, Andrea ; GRILO, Jorge ; MEACHAM, Daniel</creator><creatorcontrib>PANIGADA, Andrea ; GRILO, Jorge ; MEACHAM, Daniel</creatorcontrib><description>A circuit in an analog-to-digital converter (ADC) includes an amplifier configured to receive an output of a backend DAC; a harmonic distortion correction circuit (HDC) coupled to the amplifier and configured to correct distortion components due to the residue amplifier present in a digital signal from the backend ADC, the HDC circuit providing an output to an adder, the adder receiving a coarse digital output from a coarse ADC; and a DAC noise cancellation circuit (DNC) configured to provide an output to the adder, wherein the DNC circuit is configured to correct distortion components due to the DAC present in the digital signal from the backend ADC; wherein the output of the adder is an ADC digital output and wherein the ADC digital output forms an input to the HDC and the DNC.</description><language>eng ; fre ; ger</language><subject>BASIC ELECTRONIC CIRCUITRY ; CODE CONVERSION IN GENERAL ; CODING ; DECODING ; ELECTRICITY</subject><creationdate>2017</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20170809&amp;DB=EPODOC&amp;CC=EP&amp;NR=2719081B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,777,882,25545,76296</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20170809&amp;DB=EPODOC&amp;CC=EP&amp;NR=2719081B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>PANIGADA, Andrea</creatorcontrib><creatorcontrib>GRILO, Jorge</creatorcontrib><creatorcontrib>MEACHAM, Daniel</creatorcontrib><title>MODIFIED DYNAMIC ELEMENT MATCHING FOR REDUCED LATENCY IN A PIPELINE ANALOG TO DIGITAL CONVERTER</title><description>A circuit in an analog-to-digital converter (ADC) includes an amplifier configured to receive an output of a backend DAC; a harmonic distortion correction circuit (HDC) coupled to the amplifier and configured to correct distortion components due to the residue amplifier present in a digital signal from the backend ADC, the HDC circuit providing an output to an adder, the adder receiving a coarse digital output from a coarse ADC; and a DAC noise cancellation circuit (DNC) configured to provide an output to the adder, wherein the DNC circuit is configured to correct distortion components due to the DAC present in the digital signal from the backend ADC; wherein the output of the adder is an ADC digital output and wherein the ADC digital output forms an input to the HDC and the DNC.</description><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>CODE CONVERSION IN GENERAL</subject><subject>CODING</subject><subject>DECODING</subject><subject>ELECTRICITY</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2017</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNzDEKwkAQRuE0FqLe4b-AYLRQy3F3Egd2Z8OyEVKFIGslGoj3xxQewOo1H29Z9D5YqYQtbKfkxYAde9YET8lcRWtUISKybc2MHCVW00EUhEYadqIMUnKhRgqwUksiBxP0xjFxXBeLx_Cc8ubXVYGK5_E2j-8-T-Nwz6_86bnZH8vz7lReysMf5AupdDJP</recordid><startdate>20170809</startdate><enddate>20170809</enddate><creator>PANIGADA, Andrea</creator><creator>GRILO, Jorge</creator><creator>MEACHAM, Daniel</creator><scope>EVB</scope></search><sort><creationdate>20170809</creationdate><title>MODIFIED DYNAMIC ELEMENT MATCHING FOR REDUCED LATENCY IN A PIPELINE ANALOG TO DIGITAL CONVERTER</title><author>PANIGADA, Andrea ; GRILO, Jorge ; MEACHAM, Daniel</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP2719081B13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre ; ger</language><creationdate>2017</creationdate><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>CODE CONVERSION IN GENERAL</topic><topic>CODING</topic><topic>DECODING</topic><topic>ELECTRICITY</topic><toplevel>online_resources</toplevel><creatorcontrib>PANIGADA, Andrea</creatorcontrib><creatorcontrib>GRILO, Jorge</creatorcontrib><creatorcontrib>MEACHAM, Daniel</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>PANIGADA, Andrea</au><au>GRILO, Jorge</au><au>MEACHAM, Daniel</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>MODIFIED DYNAMIC ELEMENT MATCHING FOR REDUCED LATENCY IN A PIPELINE ANALOG TO DIGITAL CONVERTER</title><date>2017-08-09</date><risdate>2017</risdate><abstract>A circuit in an analog-to-digital converter (ADC) includes an amplifier configured to receive an output of a backend DAC; a harmonic distortion correction circuit (HDC) coupled to the amplifier and configured to correct distortion components due to the residue amplifier present in a digital signal from the backend ADC, the HDC circuit providing an output to an adder, the adder receiving a coarse digital output from a coarse ADC; and a DAC noise cancellation circuit (DNC) configured to provide an output to the adder, wherein the DNC circuit is configured to correct distortion components due to the DAC present in the digital signal from the backend ADC; wherein the output of the adder is an ADC digital output and wherein the ADC digital output forms an input to the HDC and the DNC.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRONIC CIRCUITRY
CODE CONVERSION IN GENERAL
CODING
DECODING
ELECTRICITY
title MODIFIED DYNAMIC ELEMENT MATCHING FOR REDUCED LATENCY IN A PIPELINE ANALOG TO DIGITAL CONVERTER
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-21T06%3A04%3A59IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=PANIGADA,%20Andrea&rft.date=2017-08-09&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EEP2719081B1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true