METHOD FOR RANKING PATHS FOR POWER OPTIMIZATION OF AN INTEGRATED CIRCUIT DESIGN AND CORRESPONDING COMPUTER PROGRAM PRODUCT

METHOD FOR RANKING PATHS FOR POWER OPTIMIZATION OF AN INTEGRATED CIRCUIT DESIGN AND CORRESPONDING COMPUTER PROGRAM PRODUCT

The invention pertains to a method for ranking paths for power optimization of an integrated circuit design, comprising identifying a plurality of paths of the integrated circuit design, each path comprising one or more instances of electronic devices providing an instance power estimate for each in...

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Hauptverfasser: MALACH, GAL, WEISBERGER, EYTAN, BERKOVITZ, ASHER
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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creator MALACH, GAL
WEISBERGER, EYTAN
BERKOVITZ, ASHER
description The invention pertains to a method for ranking paths for power optimization of an integrated circuit design, comprising identifying a plurality of paths of the integrated circuit design, each path comprising one or more instances of electronic devices providing an instance power estimate for each instance in the identified paths providing, for each identified path, at least one weighted power estimate based on the instance power estimates for instances in the path, and providing a ranking of the paths based on the least one weighted power estimate. The invention also pertains to a corresponding computer program product.
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subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title METHOD FOR RANKING PATHS FOR POWER OPTIMIZATION OF AN INTEGRATED CIRCUIT DESIGN AND CORRESPONDING COMPUTER PROGRAM PRODUCT
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