REFERENCE CELL ARCHITECTURES FOR SMALL MEMORY ARRAY BLOCK ACTIVATION

Systems and methods for realizing reference currents to improve reliability of sensing operations of segmented semiconductor memory arrays have been achieved. Preferred embodiments of the invention comprise MRAM arrays but the invention could be applied to any other memories requiring access on smal...

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Hauptverfasser:	CHANG, CHAO-HUNG, YUH, PERG-FEI, PU, LEJAN, SUNAGA, TOSHIO
Format:	Patent
Sprache:	eng ; fre ; ger
Schlagworte:	INFORMATION STORAGE PHYSICS STATIC STORES
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creator	CHANG, CHAO-HUNG YUH, PERG-FEI PU, LEJAN SUNAGA, TOSHIO
description	Systems and methods for realizing reference currents to improve reliability of sensing operations of segmented semiconductor memory arrays have been achieved. Preferred embodiments of the invention comprise MRAM arrays but the invention could be applied to any other memories requiring access on small, segmented arrays. All embodiments of the invention comprise a folded bit lines scheme, either in adjacent bit lines or in segment-to-segment folded bit lines. In two embodiments alternate strapping of Poly-Si Word Lines in every second segment is achieved by metal layer of Read Word Line and Write Select Line. An embodiment has stored 1 and 0 cells on both sides of a selected segment to be read.
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fullrecord	<record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_EP2630643A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>EP2630643A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_EP2630643A13</originalsourceid><addsrcrecordid>eNrjZHAJcnVzDXL1c3ZVcHb18VFwDHL28AxxdQ4JDXINVnDzD1II9nUEivu6-voHRQKlgxwjFZx8_J29FRydQzzDHEM8_f14GFjTEnOKU3mhNDeDgptriLOHbmpBfnxqcUFicmpeakm8a4CRmbGBmYmxo6ExEUoAAn8rXQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>REFERENCE CELL ARCHITECTURES FOR SMALL MEMORY ARRAY BLOCK ACTIVATION</title><source>esp@cenet</source><creator>CHANG, CHAO-HUNG ; YUH, PERG-FEI ; PU, LEJAN ; SUNAGA, TOSHIO</creator><creatorcontrib>CHANG, CHAO-HUNG ; YUH, PERG-FEI ; PU, LEJAN ; SUNAGA, TOSHIO</creatorcontrib><description>Systems and methods for realizing reference currents to improve reliability of sensing operations of segmented semiconductor memory arrays have been achieved. Preferred embodiments of the invention comprise MRAM arrays but the invention could be applied to any other memories requiring access on small, segmented arrays. All embodiments of the invention comprise a folded bit lines scheme, either in adjacent bit lines or in segment-to-segment folded bit lines. In two embodiments alternate strapping of Poly-Si Word Lines in every second segment is achieved by metal layer of Read Word Line and Write Select Line. An embodiment has stored 1 and 0 cells on both sides of a selected segment to be read.</description><language>eng ; fre ; ger</language><subject>INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2013</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20130828&DB=EPODOC&CC=EP&NR=2630643A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25563,76318</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20130828&DB=EPODOC&CC=EP&NR=2630643A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>CHANG, CHAO-HUNG</creatorcontrib><creatorcontrib>YUH, PERG-FEI</creatorcontrib><creatorcontrib>PU, LEJAN</creatorcontrib><creatorcontrib>SUNAGA, TOSHIO</creatorcontrib><title>REFERENCE CELL ARCHITECTURES FOR SMALL MEMORY ARRAY BLOCK ACTIVATION</title><description>Systems and methods for realizing reference currents to improve reliability of sensing operations of segmented semiconductor memory arrays have been achieved. Preferred embodiments of the invention comprise MRAM arrays but the invention could be applied to any other memories requiring access on small, segmented arrays. All embodiments of the invention comprise a folded bit lines scheme, either in adjacent bit lines or in segment-to-segment folded bit lines. In two embodiments alternate strapping of Poly-Si Word Lines in every second segment is achieved by metal layer of Read Word Line and Write Select Line. An embodiment has stored 1 and 0 cells on both sides of a selected segment to be read.</description><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2013</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHAJcnVzDXL1c3ZVcHb18VFwDHL28AxxdQ4JDXINVnDzD1II9nUEivu6-voHRQKlgxwjFZx8_J29FRydQzzDHEM8_f14GFjTEnOKU3mhNDeDgptriLOHbmpBfnxqcUFicmpeakm8a4CRmbGBmYmxo6ExEUoAAn8rXQ</recordid><startdate>20130828</startdate><enddate>20130828</enddate><creator>CHANG, CHAO-HUNG</creator><creator>YUH, PERG-FEI</creator><creator>PU, LEJAN</creator><creator>SUNAGA, TOSHIO</creator><scope>EVB</scope></search><sort><creationdate>20130828</creationdate><title>REFERENCE CELL ARCHITECTURES FOR SMALL MEMORY ARRAY BLOCK ACTIVATION</title><author>CHANG, CHAO-HUNG ; YUH, PERG-FEI ; PU, LEJAN ; SUNAGA, TOSHIO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP2630643A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre ; ger</language><creationdate>2013</creationdate><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>CHANG, CHAO-HUNG</creatorcontrib><creatorcontrib>YUH, PERG-FEI</creatorcontrib><creatorcontrib>PU, LEJAN</creatorcontrib><creatorcontrib>SUNAGA, TOSHIO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>CHANG, CHAO-HUNG</au><au>YUH, PERG-FEI</au><au>PU, LEJAN</au><au>SUNAGA, TOSHIO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>REFERENCE CELL ARCHITECTURES FOR SMALL MEMORY ARRAY BLOCK ACTIVATION</title><date>2013-08-28</date><risdate>2013</risdate><abstract>Systems and methods for realizing reference currents to improve reliability of sensing operations of segmented semiconductor memory arrays have been achieved. Preferred embodiments of the invention comprise MRAM arrays but the invention could be applied to any other memories requiring access on small, segmented arrays. All embodiments of the invention comprise a folded bit lines scheme, either in adjacent bit lines or in segment-to-segment folded bit lines. In two embodiments alternate strapping of Poly-Si Word Lines in every second segment is achieved by metal layer of Read Word Line and Write Select Line. An embodiment has stored 1 and 0 cells on both sides of a selected segment to be read.</abstract><oa>free_for_read</oa></addata></record>
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subjects	INFORMATION STORAGE PHYSICS STATIC STORES
title	REFERENCE CELL ARCHITECTURES FOR SMALL MEMORY ARRAY BLOCK ACTIVATION
url	https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-12T16%3A10%3A44IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=CHANG,%20CHAO-HUNG&rft.date=2013-08-28&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EEP2630643A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true