METHOD AND APPARATUS FOR IMPROVING THE EFFECT OF THE SYNCHRONOUS DIGITAL HIERARCHY VIRTUAL CONCATENATION DELAY COMPENSATION BUFFER

A method for improving the efficiency of the synchronous digital hierarchy virtual concatenation delay compensation buffer is disclosed. The method comprises: mapping the virtual containers (VCs) to the Banks of the synchronous dynamic random access memory SDRAM; writing the SDRAM write requests of the VCs into the write request first in first out (FIFO) registers of the corresponding VCs respectively; polling the write request and the read request FIFO registers of the VCs. The present invention also provides an apparatus for improving the efficiency of the synchronous digital hierarchy virtual concatenation delay compensation buffer. The present invention can reduce the invalid overhead of the SDRAM operation; thereby improve the efficiency of the SDH virtual concatenation delay compensation buffer.