METHOD FOR MANUFACTURING A REVERSE-CONDUCTING SEMICONDUCTOR DEVICE

METHOD FOR MANUFACTURING A REVERSE-CONDUCTING SEMICONDUCTOR DEVICE

For a method for manufacturing a reverse-conducting insulated gate bipolar transistor (RC-IGBT) (10) with a seventh layer (7,7') formed as a gate electrode and a first electrical contact (8) on a first main side (101) and a second electrical contact (9) on a second main side (102), which is opp...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: RAHIMO, MUNAF, JANISCH, WOLFGANG, FAGGIANO, EUSTACHIO
Format: Patent
Sprache:eng ; fre ; ger
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator RAHIMO, MUNAF
JANISCH, WOLFGANG
FAGGIANO, EUSTACHIO
description For a method for manufacturing a reverse-conducting insulated gate bipolar transistor (RC-IGBT) (10) with a seventh layer (7,7') formed as a gate electrode and a first electrical contact (8) on a first main side (101) and a second electrical contact (9) on a second main side (102), which is opposite the first main side (101), a wafer (11) of a first conductivity type with a first side (111) and a second side (112) opposite the first side (111) is provided. For the manufacturing of the RC-IGBT (10) on the second main side (112) the following steps are performed: - at least one third layer (3) of a first or second conductivity type or a ninth layer (32), which is of the same conductivity type as the third layer (3) and which is a continuous layer, is created on the second side (112) before at least one second layer (2) of a different conductivity type than the third layer (3) is created on the second side (112), the at least one second and third layers (2,3) being arranged alternately in the finalized RC-IGBT.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_EP2223341B1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>EP2223341B1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_EP2223341B13</originalsourceid><addsrcrecordid>eNrjZHDydQ3x8HdRcPMPUvB19At1c3QOCQ3y9HNXcFQIcg1zDQp21XX293MJdQ4BCQa7-npCuUANLq5hns6uPAysaYk5xam8UJqbQcHNNcTZQze1ID8-tbggMTk1L7Uk3jXAyMjI2NjE0MnQmAglAMT0Kvg</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>METHOD FOR MANUFACTURING A REVERSE-CONDUCTING SEMICONDUCTOR DEVICE</title><source>esp@cenet</source><creator>RAHIMO, MUNAF ; JANISCH, WOLFGANG ; FAGGIANO, EUSTACHIO</creator><creatorcontrib>RAHIMO, MUNAF ; JANISCH, WOLFGANG ; FAGGIANO, EUSTACHIO</creatorcontrib><description>For a method for manufacturing a reverse-conducting insulated gate bipolar transistor (RC-IGBT) (10) with a seventh layer (7,7') formed as a gate electrode and a first electrical contact (8) on a first main side (101) and a second electrical contact (9) on a second main side (102), which is opposite the first main side (101), a wafer (11) of a first conductivity type with a first side (111) and a second side (112) opposite the first side (111) is provided. For the manufacturing of the RC-IGBT (10) on the second main side (112) the following steps are performed: - at least one third layer (3) of a first or second conductivity type or a ninth layer (32), which is of the same conductivity type as the third layer (3) and which is a continuous layer, is created on the second side (112) before at least one second layer (2) of a different conductivity type than the third layer (3) is created on the second side (112), the at least one second and third layers (2,3) being arranged alternately in the finalized RC-IGBT.</description><language>eng ; fre ; ger</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2016</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20160921&amp;DB=EPODOC&amp;CC=EP&amp;NR=2223341B1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76419</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20160921&amp;DB=EPODOC&amp;CC=EP&amp;NR=2223341B1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>RAHIMO, MUNAF</creatorcontrib><creatorcontrib>JANISCH, WOLFGANG</creatorcontrib><creatorcontrib>FAGGIANO, EUSTACHIO</creatorcontrib><title>METHOD FOR MANUFACTURING A REVERSE-CONDUCTING SEMICONDUCTOR DEVICE</title><description>For a method for manufacturing a reverse-conducting insulated gate bipolar transistor (RC-IGBT) (10) with a seventh layer (7,7') formed as a gate electrode and a first electrical contact (8) on a first main side (101) and a second electrical contact (9) on a second main side (102), which is opposite the first main side (101), a wafer (11) of a first conductivity type with a first side (111) and a second side (112) opposite the first side (111) is provided. For the manufacturing of the RC-IGBT (10) on the second main side (112) the following steps are performed: - at least one third layer (3) of a first or second conductivity type or a ninth layer (32), which is of the same conductivity type as the third layer (3) and which is a continuous layer, is created on the second side (112) before at least one second layer (2) of a different conductivity type than the third layer (3) is created on the second side (112), the at least one second and third layers (2,3) being arranged alternately in the finalized RC-IGBT.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2016</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHDydQ3x8HdRcPMPUvB19At1c3QOCQ3y9HNXcFQIcg1zDQp21XX293MJdQ4BCQa7-npCuUANLq5hns6uPAysaYk5xam8UJqbQcHNNcTZQze1ID8-tbggMTk1L7Uk3jXAyMjI2NjE0MnQmAglAMT0Kvg</recordid><startdate>20160921</startdate><enddate>20160921</enddate><creator>RAHIMO, MUNAF</creator><creator>JANISCH, WOLFGANG</creator><creator>FAGGIANO, EUSTACHIO</creator><scope>EVB</scope></search><sort><creationdate>20160921</creationdate><title>METHOD FOR MANUFACTURING A REVERSE-CONDUCTING SEMICONDUCTOR DEVICE</title><author>RAHIMO, MUNAF ; JANISCH, WOLFGANG ; FAGGIANO, EUSTACHIO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP2223341B13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre ; ger</language><creationdate>2016</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>RAHIMO, MUNAF</creatorcontrib><creatorcontrib>JANISCH, WOLFGANG</creatorcontrib><creatorcontrib>FAGGIANO, EUSTACHIO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>RAHIMO, MUNAF</au><au>JANISCH, WOLFGANG</au><au>FAGGIANO, EUSTACHIO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>METHOD FOR MANUFACTURING A REVERSE-CONDUCTING SEMICONDUCTOR DEVICE</title><date>2016-09-21</date><risdate>2016</risdate><abstract>For a method for manufacturing a reverse-conducting insulated gate bipolar transistor (RC-IGBT) (10) with a seventh layer (7,7') formed as a gate electrode and a first electrical contact (8) on a first main side (101) and a second electrical contact (9) on a second main side (102), which is opposite the first main side (101), a wafer (11) of a first conductivity type with a first side (111) and a second side (112) opposite the first side (111) is provided. For the manufacturing of the RC-IGBT (10) on the second main side (112) the following steps are performed: - at least one third layer (3) of a first or second conductivity type or a ninth layer (32), which is of the same conductivity type as the third layer (3) and which is a continuous layer, is created on the second side (112) before at least one second layer (2) of a different conductivity type than the third layer (3) is created on the second side (112), the at least one second and third layers (2,3) being arranged alternately in the finalized RC-IGBT.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng ; fre ; ger
recordid cdi_epo_espacenet_EP2223341B1
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title METHOD FOR MANUFACTURING A REVERSE-CONDUCTING SEMICONDUCTOR DEVICE
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-07T22%3A23%3A42IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=RAHIMO,%20MUNAF&rft.date=2016-09-21&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EEP2223341B1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true