Method for producing interconnect structures for integrated circuits
The present invention is related to method for producing a semiconductor device comprising the steps of: - providing a semiconductor substrate (1), comprising active components on the surface of said substrate, - depositing a top layer (2) of dielectric material on the surface of said substrate or o...
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| creator | VAES, JAN VAN OLMEN, JAN HUYGHEBAERT, CEDRIC |
| description | The present invention is related to method for producing a semiconductor device comprising the steps of:
- providing a semiconductor substrate (1), comprising active components on the surface of said substrate,
- depositing a top layer (2) of dielectric material on the surface of said substrate or on other dielectric layers present on said surface,
- etching at least one first opening (7) at least through said top layer, filling said opening(s) at least with a first conductive material (8), and performing a first CMP step, to form said first conductive structures (3,26),
- etching at least one second opening (13) at least through said top layer, filling said opening(s) at least with a second conductive material (10), and performing a second CMP step, to form said second conductive structures (4,24),
wherein the method comprises the step of depositing a common CMP stopping layer (5,25) on said dielectric top layer, before the steps of etching and filling said first opening(s), so that said same CMP stopping layer is used for stopping the CMP process after filling of the first opening(s) as well as the CMP process after filling of the second opening(s). The invention is equally related to devices obtainable by the method of the invention. |
| format | Patent |
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- providing a semiconductor substrate (1), comprising active components on the surface of said substrate,
- depositing a top layer (2) of dielectric material on the surface of said substrate or on other dielectric layers present on said surface,
- etching at least one first opening (7) at least through said top layer, filling said opening(s) at least with a first conductive material (8), and performing a first CMP step, to form said first conductive structures (3,26),
- etching at least one second opening (13) at least through said top layer, filling said opening(s) at least with a second conductive material (10), and performing a second CMP step, to form said second conductive structures (4,24),
wherein the method comprises the step of depositing a common CMP stopping layer (5,25) on said dielectric top layer, before the steps of etching and filling said first opening(s), so that said same CMP stopping layer is used for stopping the CMP process after filling of the first opening(s) as well as the CMP process after filling of the second opening(s). The invention is equally related to devices obtainable by the method of the invention.</description><language>eng ; fre ; ger</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2010</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20100609&DB=EPODOC&CC=EP&NR=2194574A2$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20100609&DB=EPODOC&CC=EP&NR=2194574A2$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>VAES, JAN</creatorcontrib><creatorcontrib>VAN OLMEN, JAN</creatorcontrib><creatorcontrib>HUYGHEBAERT, CEDRIC</creatorcontrib><title>Method for producing interconnect structures for integrated circuits</title><description>The present invention is related to method for producing a semiconductor device comprising the steps of:
- providing a semiconductor substrate (1), comprising active components on the surface of said substrate,
- depositing a top layer (2) of dielectric material on the surface of said substrate or on other dielectric layers present on said surface,
- etching at least one first opening (7) at least through said top layer, filling said opening(s) at least with a first conductive material (8), and performing a first CMP step, to form said first conductive structures (3,26),
- etching at least one second opening (13) at least through said top layer, filling said opening(s) at least with a second conductive material (10), and performing a second CMP step, to form said second conductive structures (4,24),
wherein the method comprises the step of depositing a common CMP stopping layer (5,25) on said dielectric top layer, before the steps of etching and filling said first opening(s), so that said same CMP stopping layer is used for stopping the CMP process after filling of the first opening(s) as well as the CMP process after filling of the second opening(s). The invention is equally related to devices obtainable by the method of the invention.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2010</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHDxTS3JyE9RSMsvUigoyk8pTc7MS1fIzCtJLUrOz8tLTS5RKC4pKk0uKS1KLQarAsmlFyWWpKYoJGcWJZdmlhTzMLCmJeYUp_JCaW4GBTfXEGcP3dSC_PjU4oLE5NS81JJ41wAjQ0sTU3MTRyNjIpQAAMFNM2w</recordid><startdate>20100609</startdate><enddate>20100609</enddate><creator>VAES, JAN</creator><creator>VAN OLMEN, JAN</creator><creator>HUYGHEBAERT, CEDRIC</creator><scope>EVB</scope></search><sort><creationdate>20100609</creationdate><title>Method for producing interconnect structures for integrated circuits</title><author>VAES, JAN ; VAN OLMEN, JAN ; HUYGHEBAERT, CEDRIC</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_EP2194574A23</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng ; fre ; ger</language><creationdate>2010</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>VAES, JAN</creatorcontrib><creatorcontrib>VAN OLMEN, JAN</creatorcontrib><creatorcontrib>HUYGHEBAERT, CEDRIC</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>VAES, JAN</au><au>VAN OLMEN, JAN</au><au>HUYGHEBAERT, CEDRIC</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method for producing interconnect structures for integrated circuits</title><date>2010-06-09</date><risdate>2010</risdate><abstract>The present invention is related to method for producing a semiconductor device comprising the steps of:
- providing a semiconductor substrate (1), comprising active components on the surface of said substrate,
- depositing a top layer (2) of dielectric material on the surface of said substrate or on other dielectric layers present on said surface,
- etching at least one first opening (7) at least through said top layer, filling said opening(s) at least with a first conductive material (8), and performing a first CMP step, to form said first conductive structures (3,26),
- etching at least one second opening (13) at least through said top layer, filling said opening(s) at least with a second conductive material (10), and performing a second CMP step, to form said second conductive structures (4,24),
wherein the method comprises the step of depositing a common CMP stopping layer (5,25) on said dielectric top layer, before the steps of etching and filling said first opening(s), so that said same CMP stopping layer is used for stopping the CMP process after filling of the first opening(s) as well as the CMP process after filling of the second opening(s). The invention is equally related to devices obtainable by the method of the invention.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | Method for producing interconnect structures for integrated circuits |
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